riscv/rocket-chip
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fixing output enable signals for data/tag SRAMs

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This commit is contained in:
Rimas Avizienis 2011-11-12 15:47:47 -08:00
parent 83d90c4dab
commit 91c252ad08
3 changed files with 11 additions and 3 deletions
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10
rocket/src/main/scala/dcache.scala
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@ -202,6 +202,7 @@ class rocketDCacheDM(lines: Int) extends Component {
val p_store_valid = Reg(resetVal = Bool(false)); val p_store_valid = Reg(resetVal = Bool(false));
val req_store = (io.cpu.req_cmd === M_XWR); val req_store = (io.cpu.req_cmd === M_XWR);
val req_load = (io.cpu.req_cmd === M_XRD) || (io.cpu.req_cmd === M_PRD);
val r_req_load = (r_cpu_req_cmd === M_XRD) || (r_cpu_req_cmd === M_PRD); val r_req_load = (r_cpu_req_cmd === M_XRD) || (r_cpu_req_cmd === M_PRD);
val r_req_store = (r_cpu_req_cmd === M_XWR); val r_req_store = (r_cpu_req_cmd === M_XWR);
val r_req_flush = (r_cpu_req_cmd === M_FLA); val r_req_flush = (r_cpu_req_cmd === M_FLA);
@ -327,7 +328,14 @@ class rocketDCacheDM(lines: Int) extends Component {
data_array.io.d := Mux((state === s_refill), io.mem.resp_data, store_data); data_array.io.d := Mux((state === s_refill), io.mem.resp_data, store_data);
data_array.io.we := ((state === s_refill) && io.mem.resp_val) || drain_store || resolve_store; data_array.io.we := ((state === s_refill) && io.mem.resp_val) || drain_store || resolve_store;
data_array.io.bweb := Mux((state === s_refill), ~Bits(0,128), store_wmask); data_array.io.bweb := Mux((state === s_refill), ~Bits(0,128), store_wmask);
data_array.io.ce := Bool(true); // FIXME // data_array.io.ce := Bool(true); // FIXME
data_array.io.ce :=
(io.cpu.req_val && io.cpu.req_rdy && req_load) ||
(state === s_start_writeback) ||
(state === s_writeback) ||
((state === s_resolve_miss) && r_req_load) ||
(state === s_replay_load);
val data_array_rdata = data_array.io.q; val data_array_rdata = data_array.io.q;
// signal a load miss when the data isn't present in the cache and when it's in the pending store data register // signal a load miss when the data isn't present in the cache and when it's in the pending store data register

2
rocket/src/main/scala/dtlb.scala
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@ -73,7 +73,7 @@ class rocketDTLB(entries: Int) extends Component
tag_cam.io.clear := io.cpu.invalidate; tag_cam.io.clear := io.cpu.invalidate;
tag_cam.io.tag := lookup_tag; tag_cam.io.tag := lookup_tag;
tag_cam.io.write := io.ptw.resp_val; tag_cam.io.write := io.ptw.resp_val || io.ptw.resp_err;
tag_cam.io.write_tag := r_refill_tag; tag_cam.io.write_tag := r_refill_tag;
tag_cam.io.write_addr := r_refill_waddr; tag_cam.io.write_addr := r_refill_waddr;
val tag_hit = tag_cam.io.hit; val tag_hit = tag_cam.io.hit;

2
rocket/src/main/scala/itlb.scala
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@ -117,7 +117,7 @@ class rocketITLB(entries: Int) extends Component
tag_cam.io.clear := io.cpu.invalidate; tag_cam.io.clear := io.cpu.invalidate;
tag_cam.io.tag := lookup_tag; tag_cam.io.tag := lookup_tag;
tag_cam.io.write := io.ptw.resp_val; tag_cam.io.write := io.ptw.resp_val || io.ptw.resp_err;
tag_cam.io.write_tag := r_refill_tag; tag_cam.io.write_tag := r_refill_tag;
tag_cam.io.write_addr := r_refill_waddr; tag_cam.io.write_addr := r_refill_waddr;
val tag_hit = tag_cam.io.hit; val tag_hit = tag_cam.io.hit;