riscv/rocket-chip
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Grant bugfixes and more comments

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This commit is contained in:
Henry Cook
2015-04-13 15:57:06 -07:00
parent 3cf1778c92
commit 90f800d87d
2 changed files with 19 additions and 9 deletions
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3
uncore/src/main/scala/tilelink.scala
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@ -583,6 +583,7 @@ trait HasDataBeatCounters {
val cnt = Reg(init = UInt(0, width = log2Up(max+1)))
val (up_idx, do_inc) = connectDataBeatCounter(up.fire(), up.bits, beat)
val (down_idx, do_dec) = connectDataBeatCounter(down.fire(), down.bits, beat)
//Module.assert(!(do_dec && cnt === UInt(0)), "Decrementing 2way beat counter before ever incrementing")
cnt := Mux(do_dec,
Mux(do_inc, cnt, cnt - UInt(1)),
Mux(do_inc, cnt + UInt(1), cnt))
@ -632,7 +633,7 @@ class FinishUnit(srcId: Int = 0) extends TLModule
val done = connectIncomingDataBeatCounters(io.grant, entries).reduce(_||_)
val q = Module(new FinishQueue(entries))
q.io.enq.valid := io.grant.valid && g.requiresAck() && (!g.hasMultibeatData() || done)
q.io.enq.valid := io.grant.fire() && g.requiresAck() && (!g.hasMultibeatData() || done)
q.io.enq.bits.fin := g.makeFinish()
q.io.enq.bits.dst := io.grant.bits.header.src