From 90f800d87dd1d05b3837f710d9dd5d131747149e Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 13 Apr 2015 15:57:06 -0700 Subject: [PATCH] Grant bugfixes and more comments --- uncore/src/main/scala/cache.scala | 25 +++++++++++++++++-------- uncore/src/main/scala/tilelink.scala | 3 ++- 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/uncore/src/main/scala/cache.scala b/uncore/src/main/scala/cache.scala index 492ecc0e..e399eb98 100644 --- a/uncore/src/main/scala/cache.scala +++ b/uncore/src/main/scala/cache.scala @@ -577,7 +577,7 @@ class L2VoluntaryReleaseTracker(trackerId: Int, bankId: Int) extends L2XactTrack } } is(s_inner_grant) { - io.inner.grant.valid := Bool(true) + io.inner.grant.valid := !collect_irel_data when(io.inner.grant.ready) { state := Mux(io.ignt().requiresAck(), s_inner_finish, s_idle) } @@ -587,6 +587,10 @@ class L2VoluntaryReleaseTracker(trackerId: Int, bankId: Int) extends L2XactTrack when(io.inner.finish.valid) { state := s_idle } } } + + // Checks for illegal behavior + assert(!(state === s_meta_resp && io.meta.resp.valid && !io.meta.resp.bits.tag_match), + "VoluntaryReleaseTracker accepted Release for a block not resident in this cache!") } @@ -748,8 +752,7 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker { updatePendingCohWhen(io.inner.release.fire(), pending_coh_on_irel) mergeDataInner(io.inner.release) - // The following subtrascation handles misses or coherence permission - // upgrades by initiating a new transaction in the outer memory: + // Handle misses or coherence permission upgrades by initiating a new transaction in the outer memory: // // If we're allocating in this cache, we can use the current metadata // to make an appropriate custom Acquire, otherwise we copy over the @@ -804,12 +807,17 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker { pending_coh.inner.onGrant( outgoing = io.ignt(), dst = io.inner.grant.bits.header.dst), - pending_coh.outer) + Mux(ognt_data_done, + pending_coh_on_ognt.outer, + pending_coh.outer)) updatePendingCohWhen(io.inner.grant.fire(), pending_coh_on_ignt) // We must wait for as many Finishes as we sent Grants io.inner.finish.ready := state === s_busy + // We read from the the cache at this level if data wasn't written back or refilled. + // We may merge Gets, requiring further beats to be read. + // If ECC requires a full writemask, we'll read out data on partial writes as well. pending_reads := (pending_reads & dropPendingBit(io.data.read) & dropPendingBitWhenBeatHasData(io.inner.release) & @@ -829,6 +837,8 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker { addPendingBitInternal(io.data.read) mergeDataInternal(io.data.resp) + // We write data to the cache at this level if it was Put here with allocate flag, + // written back dirty, or refilled from outer memory. pending_writes := (pending_writes & dropPendingBit(io.data.write)) | addPendingBitWhenBeatHasData(io.inner.acquire) | addPendingBitWhenBeatHasData(io.inner.release) | @@ -883,11 +893,11 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker { xact_src := io.inner.acquire.bits.header.src xact := io.iacq() xact.data := UInt(0) - pending_puts := Mux( + pending_puts := Mux( // Make sure to collect all data from a PutBlock io.iacq().isBuiltInType(Acquire.putBlockType), dropPendingBitWhenBeatHasData(io.inner.acquire), UInt(0)) - pending_reads := Mux( + pending_reads := Mux( // GetBlocks and custom types read all beats io.iacq().isBuiltInType(Acquire.getBlockType) || !io.iacq().isBuiltInType(), SInt(-1, width = innerDataBeats), (addPendingBitWhenBeatIsGetOrAtomic(io.inner.acquire) | @@ -932,8 +942,7 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker { when(state === s_wb_resp && io.wb.resp.valid) { // If we're overwriting the whole block in a last level cache we can // just do it without fetching any data from memory - val skip_outer_acquire = Bool(isLastLevelCache) && - xact.isBuiltInType(Acquire.putBlockType) + val skip_outer_acquire = Bool(isLastLevelCache) && xact.isBuiltInType(Acquire.putBlockType) state := Mux(!skip_outer_acquire, s_outer_acquire, s_busy) } when(state === s_inner_probe && !(pending_iprbs.orR || pending_irels)) { diff --git a/uncore/src/main/scala/tilelink.scala b/uncore/src/main/scala/tilelink.scala index c2bc2d30..d639f791 100644 --- a/uncore/src/main/scala/tilelink.scala +++ b/uncore/src/main/scala/tilelink.scala @@ -583,6 +583,7 @@ trait HasDataBeatCounters { val cnt = Reg(init = UInt(0, width = log2Up(max+1))) val (up_idx, do_inc) = connectDataBeatCounter(up.fire(), up.bits, beat) val (down_idx, do_dec) = connectDataBeatCounter(down.fire(), down.bits, beat) + //Module.assert(!(do_dec && cnt === UInt(0)), "Decrementing 2way beat counter before ever incrementing") cnt := Mux(do_dec, Mux(do_inc, cnt, cnt - UInt(1)), Mux(do_inc, cnt + UInt(1), cnt)) @@ -632,7 +633,7 @@ class FinishUnit(srcId: Int = 0) extends TLModule val done = connectIncomingDataBeatCounters(io.grant, entries).reduce(_||_) val q = Module(new FinishQueue(entries)) - q.io.enq.valid := io.grant.valid && g.requiresAck() && (!g.hasMultibeatData() || done) + q.io.enq.valid := io.grant.fire() && g.requiresAck() && (!g.hasMultibeatData() || done) q.io.enq.bits.fin := g.makeFinish() q.io.enq.bits.dst := io.grant.bits.header.src