riscv/rocket-chip
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first pass at configuration object passed as implicit parameter

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This commit is contained in:
Henry Cook
2012-10-07 22:37:29 -07:00
parent dfdfddebe8
commit 9025d0610c
8 changed files with 57 additions and 55 deletions
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8
rocket/src/main/scala/tile.scala
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@ -5,7 +5,7 @@ import Node._
import Constants._
import uncore._
class Tile(co: CoherencePolicyWithUncached, resetSignal: Bool = null) extends Component(resetSignal)
class Tile(resetSignal: Bool = null)(implicit conf: Configuration) extends Component(resetSignal)
{
val io = new Bundle {
val tilelink = new ioTileLink
@ -13,8 +13,8 @@ class Tile(co: CoherencePolicyWithUncached, resetSignal: Bool = null) extends Co
}
val cpu = new rocketProc
val icache = new rocketICache(128, 4, co) // 128 sets x 4 ways (32KB)
val dcache = new HellaCache(co)
val icache = new rocketICache(128, 4) // 128 sets x 4 ways (32KB)
val dcache = new HellaCache
val arbiter = new rocketMemArbiter(2 + (if (HAVE_VEC) 1 else 0))
arbiter.io.requestor(0) <> dcache.io.mem
@ -31,7 +31,7 @@ class Tile(co: CoherencePolicyWithUncached, resetSignal: Bool = null) extends Co
if (HAVE_VEC)
{
val vicache = new rocketICache(128, 1, co) // 128 sets x 1 ways (8KB)
val vicache = new rocketICache(128, 1) // 128 sets x 1 ways (8KB)
arbiter.io.requestor(2) <> vicache.io.mem
cpu.io.vimem <> vicache.io.cpu
}