diff --git a/rocket/src/main/scala/cpu.scala b/rocket/src/main/scala/cpu.scala
index c0a2f1c7..412d7e11 100644
--- a/rocket/src/main/scala/cpu.scala
+++ b/rocket/src/main/scala/cpu.scala
@@ -1,19 +1,19 @@
 package rocket
 
-import Chisel._;
-import Node._;
-import Constants._;
+import Chisel._
+import Node._
+import Constants._
 import hwacha._
 
-class ioRocket extends Bundle()
+class ioRocket()(implicit conf: Configuration) extends Bundle
 {
-  val host    = new ioHTIF
+  val host    = new ioHTIF()
   val imem    = (new ioImem).flip
   val vimem   = (new ioImem).flip
   val dmem    = new ioHellaCache
 }
 
-class rocketProc extends Component
+class rocketProc()(implicit conf: Configuration) extends Component
 {
   val io    = new ioRocket
    
diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala
index a4d259c8..fc199520 100644
--- a/rocket/src/main/scala/dpath.scala
+++ b/rocket/src/main/scala/dpath.scala
@@ -12,9 +12,9 @@ class ioDpathImem extends Bundle()
   val resp_data = Bits(INPUT, 32);
 }
 
-class ioDpathAll extends Bundle()
+class ioDpathAll()(implicit conf: Configuration) extends Bundle()
 {
-  val host  = new ioHTIF();
+  val host  = new ioHTIF()
   val ctrl  = new ioCtrlDpath().flip
   val dmem = new ioHellaCache
   val dtlb = new ioDTLB_CPU_req_bundle().asOutput()
@@ -28,7 +28,7 @@ class ioDpathAll extends Bundle()
   val vec_imul_resp = Bits(INPUT, hwacha.Constants.SZ_XLEN)
 }
 
-class rocketDpath extends Component
+class rocketDpath()(implicit conf: Configuration) extends Component
 {
   val io  = new ioDpathAll();
   
diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala
index e648a1e2..66e6dec9 100644
--- a/rocket/src/main/scala/dpath_util.scala
+++ b/rocket/src/main/scala/dpath_util.scala
@@ -57,7 +57,7 @@ class rocketDpathBTB(entries: Int) extends Component
   io.target := mux.io.out.toUFix
 }
 
-class ioDpathPCR extends Bundle()
+class ioDpathPCR()(implicit conf: Configuration) extends Bundle()
 {
   val host  = new ioHTIF()
   val r     = new ioReadPort();
@@ -86,7 +86,7 @@ class ioDpathPCR extends Bundle()
   val vec_nfregs = UFix(INPUT, 6)
 }
 
-class rocketDpathPCR extends Component
+class rocketDpathPCR()(implicit conf: Configuration) extends Component
 {
   val io = new ioDpathPCR();
   
diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala
index 33a56c56..761bb59d 100644
--- a/rocket/src/main/scala/htif.scala
+++ b/rocket/src/main/scala/htif.scala
@@ -23,21 +23,21 @@ class PCRReq extends Bundle
   val data = Bits(width = 64)
 }
 
-class ioHTIF extends Bundle
+class ioHTIF()(implicit conf: Configuration) extends Bundle
 {
   val reset = Bool(INPUT)
   val debug = new ioDebug
   val pcr_req = (new FIFOIO) { new PCRReq }.flip
   val pcr_rep = (new FIFOIO) { Bits(width = 64) }
-  val ipi_req = (new FIFOIO) { Bits(width = log2Up(NTILES)) }
+  val ipi_req = (new FIFOIO) { Bits(width = log2Up(conf.ntiles)) }
   val ipi_rep = (new FIFOIO) { Bool() }.flip
 }
 
-class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends Component
+class rocketHTIF(w: Int)(implicit conf: Configuration) extends Component
 {
   val io = new Bundle {
     val host = new ioHost(w)
-    val cpu = Vec(ncores) { new ioHTIF().flip }
+    val cpu = Vec(conf.ntiles) { new ioHTIF().flip }
     val mem = new ioTileLink
   }
 
@@ -78,7 +78,7 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
   val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(6) { UFix() }
 
   val pcr_addr = addr(io.cpu(0).pcr_req.bits.addr.width-1, 0)
-  val pcr_coreid = if (ncores == 1) UFix(0) else addr(20+log2Up(ncores),20)
+  val pcr_coreid = if (conf.ntiles == 1) UFix(0) else addr(20+log2Up(conf.ntiles),20)
   val pcr_wdata = packet_ram(0)
 
   val bad_mem_packet = size(OFFSET_BITS-1-3,0).orR || addr(OFFSET_BITS-1-3,0).orR
@@ -178,7 +178,7 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
   }
   x_init.io.enq.valid := state === state_mem_req
   val init_addr = addr.toUFix >> UFix(OFFSET_BITS-3)
-  x_init.io.enq.bits := Mux(cmd === cmd_writemem, co.getUncachedWriteTransactionInit(init_addr, UFix(0)), co.getUncachedReadTransactionInit(init_addr, UFix(0)))
+  x_init.io.enq.bits := Mux(cmd === cmd_writemem, conf.co.getUncachedWriteTransactionInit(init_addr, UFix(0)), conf.co.getUncachedReadTransactionInit(init_addr, UFix(0)))
   io.mem.xact_init <> x_init.io.deq
   io.mem.xact_init_data.valid:= state === state_mem_wdata
   io.mem.xact_init_data.bits.data := mem_req_data
@@ -189,8 +189,8 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
   io.mem.probe_rep_data.valid := Bool(false)
   io.mem.incoherent := Bool(true)
 
-  val pcr_mux = (new Mux1H(ncores)) { Bits(width = 64) }
-  for (i <- 0 until ncores) {
+  val pcr_mux = (new Mux1H(conf.ntiles)) { Bits(width = 64) }
+  for (i <- 0 until conf.ntiles) {
     val my_reset = Reg(resetVal = Bool(true))
     val my_ipi = Reg(resetVal = Bool(false))
     val rdata = Reg() { Bits() }
@@ -208,7 +208,7 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
     }
     cpu.ipi_rep.valid := my_ipi
     cpu.ipi_req.ready := Bool(true)
-    for (j <- 0 until ncores) {
+    for (j <- 0 until conf.ntiles) {
       when (io.cpu(j).ipi_req.valid && io.cpu(j).ipi_req.bits === UFix(i)) {
         my_ipi := Bool(true)
       }
diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index eb4c4b80..c0fa675e 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -28,7 +28,7 @@ class ioRocketICache extends Bundle()
 // 32 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines
 // parameters :
 //    lines = # cache lines
-class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) extends Component
+class rocketICache(sets: Int, assoc: Int)(implicit conf: Configuration)  extends Component
 {
   val io = new ioRocketICache();
 
@@ -137,7 +137,7 @@ class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) exten
   rdy := !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || tag_hit);
   io.cpu.resp_data := data_mux.io.out
   io.mem.xact_init.valid := (state === s_request) && finish_q.io.enq.ready
-  io.mem.xact_init.bits := co.getUncachedReadTransactionInit(r_cpu_miss_addr(tagmsb,indexlsb).toUFix, UFix(0))
+  io.mem.xact_init.bits := conf.co.getUncachedReadTransactionInit(r_cpu_miss_addr(tagmsb,indexlsb).toUFix, UFix(0))
   io.mem.xact_finish <> finish_q.io.deq
 
   // control state machine
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index 951d6adc..a2f0839a 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -159,7 +159,7 @@ class MetaArrayReq extends Bundle {
   val data = new MetaData()
 }
 
-class MSHR(id: Int, co: CoherencePolicy) extends Component {
+class MSHR(id: Int)(implicit conf: Configuration) extends Component {
   val io = new Bundle {
     val req_pri_val    = Bool(INPUT)
     val req_pri_rdy    = Bool(OUTPUT)
@@ -197,7 +197,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
   val req_cmd = io.req_bits.cmd
   val req_use_rpq = (req_cmd != M_PFR) && (req_cmd != M_PFW) && (req_cmd != M_FLA)
   val idx_match = req.idx === io.req_bits.idx
-  val sec_rdy = idx_match && !flush && (state === s_wb_req || state === s_wb_resp || state === s_meta_clear || (state === s_refill_req || state === s_refill_resp) && !co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits))
+  val sec_rdy = idx_match && !flush && (state === s_wb_req || state === s_wb_resp || state === s_meta_clear || (state === s_refill_req || state === s_refill_resp) && !conf.co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits))
 
   val rpq = (new Queue(NRPQ)) { new RPQEntry }
   rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy || io.req_sec_val && sec_rdy) && req_use_rpq
@@ -221,7 +221,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
     when (refill_done) { state := s_drain_rpq }
     when (reply) {
       refill_count := refill_count + UFix(1)
-      line_state := co.newStateOnTransactionReply(io.mem_rep.bits, io.mem_req.bits)
+      line_state := conf.co.newStateOnTransactionReply(io.mem_rep.bits, io.mem_req.bits)
     }
     when (abort) { state := s_refill_req }
   }
@@ -243,13 +243,13 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
   }
 
   when (io.req_sec_val && io.req_sec_rdy) { // s_wb_req, s_wb_resp, s_refill_req
-    xacx_type := co.getTransactionInitTypeOnSecondaryMiss(req_cmd, co.newStateOnFlush(), io.mem_req.bits)
+    xacx_type := conf.co.getTransactionInitTypeOnSecondaryMiss(req_cmd, conf.co.newStateOnFlush(), io.mem_req.bits)
   }
   when ((state === s_invalid) && io.req_pri_val) {
     flush := req_cmd === M_FLA
-    line_state := co.newStateOnFlush()
+    line_state := conf.co.newStateOnFlush()
     refill_count := UFix(0)
-    xacx_type := co.getTransactionInitTypeOnPrimaryMiss(req_cmd, co.newStateOnFlush())
+    xacx_type := conf.co.getTransactionInitTypeOnPrimaryMiss(req_cmd, conf.co.newStateOnFlush())
     req := io.req_bits
 
     when (io.req_bits.tag_miss) {
@@ -268,7 +268,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
   io.meta_req.valid := (state === s_drain_rpq) && !rpq.io.deq.valid && !finish_q.io.deq.valid || (state === s_meta_clear)
   io.meta_req.bits.rw := Bool(true)
   io.meta_req.bits.idx := req.idx
-  io.meta_req.bits.data.state := Mux(state === s_meta_clear, co.newStateOnFlush(), line_state)
+  io.meta_req.bits.data.state := Mux(state === s_meta_clear, conf.co.newStateOnFlush(), line_state)
   io.meta_req.bits.data.tag := req.tag
   io.meta_req.bits.way_en := req.way_oh
 
@@ -293,7 +293,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
   io.replay.bits.way_oh := req.way_oh
 }
 
-class MSHRFile(co: CoherencePolicy) extends Component {
+class MSHRFile()(implicit conf: Configuration) extends Component {
   val io = new Bundle {
     val req = (new FIFOIO) { new MSHRReq }.flip
     val secondary_miss = Bool(OUTPUT)
@@ -346,7 +346,7 @@ class MSHRFile(co: CoherencePolicy) extends Component {
   var refill_probe_rdy = Bool(true)
 
   for (i <- 0 to NMSHR-1) {
-    val mshr = new MSHR(i, co)
+    val mshr = new MSHR(i)
 
     tag_mux.io.sel(i) := mshr.io.idx_match
     tag_mux.io.in(i) := mshr.io.tag
@@ -415,7 +415,7 @@ class MSHRFile(co: CoherencePolicy) extends Component {
 }
 
 
-class WritebackUnit(co: CoherencePolicy) extends Component {
+class WritebackUnit()(implicit conf: Configuration) extends Component {
   val io = new Bundle {
     val req = (new FIFOIO) { new WritebackReq() }.flip
     val probe = (new FIFOIO) { new WritebackReq() }.flip
@@ -475,7 +475,7 @@ class WritebackUnit(co: CoherencePolicy) extends Component {
   io.data_req.bits.data := Bits(0)
 
   io.mem_req.valid := valid && !cmd_sent
-  io.mem_req.bits.x_type := co.getTransactionInitTypeOnWriteback()
+  io.mem_req.bits.x_type := conf.co.getTransactionInitTypeOnWriteback()
   io.mem_req.bits.addr := Cat(req.tag, req.idx).toUFix
   io.mem_req.bits.tile_xact_id := req.tile_xact_id
   io.mem_req_data.valid := data_req_fired && !is_probe
@@ -484,7 +484,7 @@ class WritebackUnit(co: CoherencePolicy) extends Component {
   io.probe_rep_data.bits.data := io.data_resp
 }
 
-class ProbeUnit(co: CoherencePolicy) extends Component {
+class ProbeUnit()(implicit conf: Configuration)  extends Component {
   val io = new Bundle {
     val req = (new FIFOIO) { new ProbeRequest }.flip
     val rep = (new FIFOIO) { new ProbeReply }
@@ -510,7 +510,7 @@ class ProbeUnit(co: CoherencePolicy) extends Component {
     state := s_writeback_resp
   }
   when ((state === s_probe_rep) && io.meta_req.ready && io.rep.ready) {
-    state := Mux(hit && co.needsWriteback(line_state), s_writeback_req, s_invalid)
+    state := Mux(hit && conf.co.needsWriteback(line_state), s_writeback_req, s_invalid)
   }
   when ((state === s_mshr_req) && io.mshr_req.ready) {
     state := s_meta_req
@@ -531,13 +531,13 @@ class ProbeUnit(co: CoherencePolicy) extends Component {
 
   io.req.ready := state === s_invalid
   io.rep.valid := state === s_probe_rep && io.meta_req.ready
-  io.rep.bits := co.newProbeReply(req, Mux(hit, line_state, co.newStateOnFlush()))
+  io.rep.bits := conf.co.newProbeReply(req, Mux(hit, line_state, conf.co.newStateOnFlush))
 
   io.meta_req.valid := state === s_meta_req || state === s_meta_resp || state === s_mshr_req || state === s_probe_rep && hit
   io.meta_req.bits.way_en := Mux(state === s_probe_rep, way_oh, ~UFix(0, NWAYS))
   io.meta_req.bits.rw := state === s_probe_rep
   io.meta_req.bits.idx := req.addr
-  io.meta_req.bits.data.state := co.newStateOnProbeRequest(req, line_state)
+  io.meta_req.bits.data.state := conf.co.newStateOnProbeRequest(req, line_state)
   io.meta_req.bits.data.tag := req.addr >> UFix(IDX_BITS)
   io.mshr_req.valid := state === s_meta_resp || state === s_mshr_req
   io.addr := req.addr
@@ -548,7 +548,7 @@ class ProbeUnit(co: CoherencePolicy) extends Component {
   io.wb_req.bits.tag := req.addr >> UFix(IDX_BITS)
 }
 
-class FlushUnit(lines: Int, co: CoherencePolicy) extends Component {
+class FlushUnit(lines: Int)(implicit conf: Configuration) extends Component {
   val io = new Bundle {
     val req = (new FIFOIO) { Bool() }.flip
     val meta_req = (new FIFOIO) { new MetaArrayReq() }
@@ -593,7 +593,7 @@ class FlushUnit(lines: Int, co: CoherencePolicy) extends Component {
   io.meta_req.bits.way_en := UFixToOH(way_cnt, NWAYS)
   io.meta_req.bits.idx := idx_cnt
   io.meta_req.bits.rw := (state === s_reset)
-  io.meta_req.bits.data.state := co.newStateOnFlush()
+  io.meta_req.bits.data.state := conf.co.newStateOnFlush()
   io.meta_req.bits.data.tag := UFix(0)
 }
 
@@ -748,7 +748,7 @@ class ioHellaCache extends Bundle {
   val xcpt = (new HellaCacheExceptions).asInput
 }
 
-class HellaCache(co: CoherencePolicy) extends Component {
+class HellaCache()(implicit conf: Configuration) extends Component {
   val io = new Bundle {
     val cpu = (new ioHellaCache).flip
     val mem = new ioTileLink
@@ -801,10 +801,10 @@ class HellaCache(co: CoherencePolicy) extends Component {
   val r_req_readwrite = r_req_read || r_req_write || r_req_prefetch
   val nack_hit = Bool()
 
-  val wb = new WritebackUnit(co)
-  val prober = new ProbeUnit(co)
-  val mshr = new MSHRFile(co)
-  val flusher = new FlushUnit(lines, co)
+  val wb = new WritebackUnit
+  val prober = new ProbeUnit
+  val mshr = new MSHRFile
+  val flusher = new FlushUnit(lines)
   val replay_amo_val = mshr.io.data_req.valid && mshr.io.data_req.bits.cmd(3).toBool
 
   // reset and flush unit
@@ -863,10 +863,10 @@ class HellaCache(co: CoherencePolicy) extends Component {
   val early_tag_nack = !meta_arb.io.in(3).ready
   val cpu_req_ppn = Mux(prober.io.mshr_req.valid, prober.io.addr >> UFix(PGIDX_BITS-OFFSET_BITS), io.cpu.req.bits.ppn)
   val cpu_req_tag = Cat(cpu_req_ppn, r_cpu_req_idx)(tagmsb,taglsb)
-  val tag_match_arr = (0 until NWAYS).map( w => co.isValid(meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag))
+  val tag_match_arr = (0 until NWAYS).map( w => conf.co.isValid(meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag))
   val tag_match = Cat(Bits(0),tag_match_arr:_*).orR
   val tag_match_way_oh = Cat(Bits(0),tag_match_arr.reverse:_*)(NWAYS-1, 0) //TODO: use Vec
-  val tag_hit_arr = (0 until NWAYS).map( w => co.isHit(r_cpu_req_cmd, meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag))
+  val tag_hit_arr = (0 until NWAYS).map( w => conf.co.isHit(r_cpu_req_cmd, meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag))
   val tag_hit = Cat(Bits(0),tag_hit_arr:_*).orR
   val meta_resp_way_oh = Mux(meta.io.way_en === ~UFix(0, NWAYS), tag_match_way_oh, meta.io.way_en)
   val data_resp_way_oh = Mux(data.io.way_en === ~UFix(0, NWAYS), tag_match_way_oh, data.io.way_en)
@@ -892,7 +892,7 @@ class HellaCache(co: CoherencePolicy) extends Component {
   data_arb.io.in(0).bits.wmask := ~UFix(0, MEM_DATA_BITS/8)
   data_arb.io.in(0).bits.data := io.mem.xact_rep.bits.data
   data_arb.io.in(0).bits.way_en := mshr.io.mem_resp_way_oh
-  data_arb.io.in(0).valid := io.mem.xact_rep.valid && co.messageUpdatesDataArray(io.mem.xact_rep.bits)
+  data_arb.io.in(0).valid := io.mem.xact_rep.valid && conf.co.messageUpdatesDataArray(io.mem.xact_rep.bits)
 
   // load hits
   data_arb.io.in(4).bits.offset := io.cpu.req.bits.idx(offsetmsb,ramindexlsb)
@@ -922,7 +922,7 @@ class HellaCache(co: CoherencePolicy) extends Component {
   p_store_valid := p_store_valid && !drain_store || (r_cpu_req_val && tag_hit && r_req_store && mshr.io.req.ready && !nack_hit) || p_amo
 
   // tag update after a store to an exclusive clean line.
-  val new_hit_state = co.newStateOnHit(r_cpu_req_cmd, meta_resp_mux.state)
+  val new_hit_state = conf.co.newStateOnHit(r_cpu_req_cmd, meta_resp_mux.state)
   val set_hit_state  = r_cpu_req_val && tag_hit && meta_resp_mux.state != new_hit_state
   meta.io.state_req.bits.rw := Bool(true)
   meta.io.state_req.bits.idx := Reg(r_cpu_req_idx(indexmsb,indexlsb))
@@ -946,7 +946,7 @@ class HellaCache(co: CoherencePolicy) extends Component {
   // miss handling
   mshr.io.req.valid := r_cpu_req_val && r_req_readwrite && !nack_hit || flusher.io.mshr_req.valid
   mshr.io.req.bits.tag_miss := !tag_hit || flusher.io.mshr_req.valid
-  mshr.io.req.bits.old_dirty := co.needsWriteback(meta_wb_mux.state) && (!tag_match || flusher.io.mshr_req.valid) // don't wb upgrades
+  mshr.io.req.bits.old_dirty := conf.co.needsWriteback(meta_wb_mux.state) && (!tag_match || flusher.io.mshr_req.valid) // don't wb upgrades
   mshr.io.req.bits.old_tag := meta_wb_mux.tag
   mshr.io.req.bits.tag := cpu_req_tag
   mshr.io.req.bits.idx := r_cpu_req_idx(indexmsb,indexlsb)
diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala
index 5e621808..30e961d6 100644
--- a/rocket/src/main/scala/tile.scala
+++ b/rocket/src/main/scala/tile.scala
@@ -5,7 +5,7 @@ import Node._
 import Constants._
 import uncore._
 
-class Tile(co: CoherencePolicyWithUncached, resetSignal: Bool = null) extends Component(resetSignal)
+class Tile(resetSignal: Bool = null)(implicit conf: Configuration) extends Component(resetSignal)
 {
   val io = new Bundle {
     val tilelink = new ioTileLink
@@ -13,8 +13,8 @@ class Tile(co: CoherencePolicyWithUncached, resetSignal: Bool = null) extends Co
   }
   
   val cpu       = new rocketProc
-  val icache    = new rocketICache(128, 4, co) // 128 sets x 4 ways (32KB)
-  val dcache    = new HellaCache(co)
+  val icache    = new rocketICache(128, 4) // 128 sets x 4 ways (32KB)
+  val dcache    = new HellaCache
 
   val arbiter   = new rocketMemArbiter(2 + (if (HAVE_VEC) 1 else 0))
   arbiter.io.requestor(0) <> dcache.io.mem
@@ -31,7 +31,7 @@ class Tile(co: CoherencePolicyWithUncached, resetSignal: Bool = null) extends Co
 
   if (HAVE_VEC)
   {
-    val vicache = new rocketICache(128, 1, co) // 128 sets x 1 ways (8KB)
+    val vicache = new rocketICache(128, 1) // 128 sets x 1 ways (8KB)
     arbiter.io.requestor(2) <> vicache.io.mem
     cpu.io.vimem <> vicache.io.cpu
   }
diff --git a/rocket/src/main/scala/top.scala b/rocket/src/main/scala/top.scala
index 42413045..35c41e79 100644
--- a/rocket/src/main/scala/top.scala
+++ b/rocket/src/main/scala/top.scala
@@ -13,6 +13,7 @@ object DummyTopLevelConstants extends rocket.constants.CoherenceConfigConstants
 }
 import DummyTopLevelConstants._
 
+case class Configuration(ntiles: Int, co: CoherencePolicyWithUncached)
 
 class Top extends Component 
 {
@@ -23,6 +24,7 @@ class Top extends Component
               if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence
               else new MICoherence
             }
+  implicit val conf = Configuration(NTILES, co)
 
   val io = new Bundle  {
     val debug   = new ioDebug
@@ -30,7 +32,7 @@ class Top extends Component
     val mem     = new ioMemPipe
   }
 
-  val htif = new rocketHTIF(HTIF_WIDTH, NTILES, co)
+  val htif = new rocketHTIF(HTIF_WIDTH)
   val hub = new CoherenceHubBroadcast(NTILES+1, co)
   hub.io.tiles(NTILES) <> htif.io.mem
   io.host <> htif.io.host
@@ -44,7 +46,7 @@ class Top extends Component
   for (i <- 0 until NTILES) {
     val hl = htif.io.cpu(i)
     val tl = hub.io.tiles(i)
-    val tile = new Tile(co, resetSignal = hl.reset)
+    val tile = new Tile(resetSignal = hl.reset)
 
     tile.io.host.reset := Reg(Reg(hl.reset))
     tile.io.host.pcr_req <> Queue(hl.pcr_req)