riscv/rocket-chip
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first pass at configuration object passed as implicit parameter

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This commit is contained in:
Henry Cook
2012-10-07 22:37:29 -07:00
parent dfdfddebe8
commit 9025d0610c
8 changed files with 57 additions and 55 deletions
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54
rocket/src/main/scala/nbdcache.scala
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@ -159,7 +159,7 @@ class MetaArrayReq extends Bundle {
val data = new MetaData()
}
class MSHR(id: Int, co: CoherencePolicy) extends Component {
class MSHR(id: Int)(implicit conf: Configuration) extends Component {
val io = new Bundle {
val req_pri_val = Bool(INPUT)
val req_pri_rdy = Bool(OUTPUT)
@ -197,7 +197,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
val req_cmd = io.req_bits.cmd
val req_use_rpq = (req_cmd != M_PFR) && (req_cmd != M_PFW) && (req_cmd != M_FLA)
val idx_match = req.idx === io.req_bits.idx
val sec_rdy = idx_match && !flush && (state === s_wb_req || state === s_wb_resp || state === s_meta_clear || (state === s_refill_req || state === s_refill_resp) && !co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits))
val sec_rdy = idx_match && !flush && (state === s_wb_req || state === s_wb_resp || state === s_meta_clear || (state === s_refill_req || state === s_refill_resp) && !conf.co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits))
val rpq = (new Queue(NRPQ)) { new RPQEntry }
rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy || io.req_sec_val && sec_rdy) && req_use_rpq
@ -221,7 +221,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
when (refill_done) { state := s_drain_rpq }
when (reply) {
refill_count := refill_count + UFix(1)
line_state := co.newStateOnTransactionReply(io.mem_rep.bits, io.mem_req.bits)
line_state := conf.co.newStateOnTransactionReply(io.mem_rep.bits, io.mem_req.bits)
}
when (abort) { state := s_refill_req }
}
@ -243,13 +243,13 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
}
when (io.req_sec_val && io.req_sec_rdy) { // s_wb_req, s_wb_resp, s_refill_req
xacx_type := co.getTransactionInitTypeOnSecondaryMiss(req_cmd, co.newStateOnFlush(), io.mem_req.bits)
xacx_type := conf.co.getTransactionInitTypeOnSecondaryMiss(req_cmd, conf.co.newStateOnFlush(), io.mem_req.bits)
}
when ((state === s_invalid) && io.req_pri_val) {
flush := req_cmd === M_FLA
line_state := co.newStateOnFlush()
line_state := conf.co.newStateOnFlush()
refill_count := UFix(0)
xacx_type := co.getTransactionInitTypeOnPrimaryMiss(req_cmd, co.newStateOnFlush())
xacx_type := conf.co.getTransactionInitTypeOnPrimaryMiss(req_cmd, conf.co.newStateOnFlush())
req := io.req_bits
when (io.req_bits.tag_miss) {
@ -268,7 +268,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
io.meta_req.valid := (state === s_drain_rpq) && !rpq.io.deq.valid && !finish_q.io.deq.valid || (state === s_meta_clear)
io.meta_req.bits.rw := Bool(true)
io.meta_req.bits.idx := req.idx
io.meta_req.bits.data.state := Mux(state === s_meta_clear, co.newStateOnFlush(), line_state)
io.meta_req.bits.data.state := Mux(state === s_meta_clear, conf.co.newStateOnFlush(), line_state)
io.meta_req.bits.data.tag := req.tag
io.meta_req.bits.way_en := req.way_oh
@ -293,7 +293,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
io.replay.bits.way_oh := req.way_oh
}
class MSHRFile(co: CoherencePolicy) extends Component {
class MSHRFile()(implicit conf: Configuration) extends Component {
val io = new Bundle {
val req = (new FIFOIO) { new MSHRReq }.flip
val secondary_miss = Bool(OUTPUT)
@ -346,7 +346,7 @@ class MSHRFile(co: CoherencePolicy) extends Component {
var refill_probe_rdy = Bool(true)
for (i <- 0 to NMSHR-1) {
val mshr = new MSHR(i, co)
val mshr = new MSHR(i)
tag_mux.io.sel(i) := mshr.io.idx_match
tag_mux.io.in(i) := mshr.io.tag
@ -415,7 +415,7 @@ class MSHRFile(co: CoherencePolicy) extends Component {
}
class WritebackUnit(co: CoherencePolicy) extends Component {
class WritebackUnit()(implicit conf: Configuration) extends Component {
val io = new Bundle {
val req = (new FIFOIO) { new WritebackReq() }.flip
val probe = (new FIFOIO) { new WritebackReq() }.flip
@ -475,7 +475,7 @@ class WritebackUnit(co: CoherencePolicy) extends Component {
io.data_req.bits.data := Bits(0)
io.mem_req.valid := valid && !cmd_sent
io.mem_req.bits.x_type := co.getTransactionInitTypeOnWriteback()
io.mem_req.bits.x_type := conf.co.getTransactionInitTypeOnWriteback()
io.mem_req.bits.addr := Cat(req.tag, req.idx).toUFix
io.mem_req.bits.tile_xact_id := req.tile_xact_id
io.mem_req_data.valid := data_req_fired && !is_probe
@ -484,7 +484,7 @@ class WritebackUnit(co: CoherencePolicy) extends Component {
io.probe_rep_data.bits.data := io.data_resp
}
class ProbeUnit(co: CoherencePolicy) extends Component {
class ProbeUnit()(implicit conf: Configuration) extends Component {
val io = new Bundle {
val req = (new FIFOIO) { new ProbeRequest }.flip
val rep = (new FIFOIO) { new ProbeReply }
@ -510,7 +510,7 @@ class ProbeUnit(co: CoherencePolicy) extends Component {
state := s_writeback_resp
}
when ((state === s_probe_rep) && io.meta_req.ready && io.rep.ready) {
state := Mux(hit && co.needsWriteback(line_state), s_writeback_req, s_invalid)
state := Mux(hit && conf.co.needsWriteback(line_state), s_writeback_req, s_invalid)
}
when ((state === s_mshr_req) && io.mshr_req.ready) {
state := s_meta_req
@ -531,13 +531,13 @@ class ProbeUnit(co: CoherencePolicy) extends Component {
io.req.ready := state === s_invalid
io.rep.valid := state === s_probe_rep && io.meta_req.ready
io.rep.bits := co.newProbeReply(req, Mux(hit, line_state, co.newStateOnFlush()))
io.rep.bits := conf.co.newProbeReply(req, Mux(hit, line_state, conf.co.newStateOnFlush))
io.meta_req.valid := state === s_meta_req || state === s_meta_resp || state === s_mshr_req || state === s_probe_rep && hit
io.meta_req.bits.way_en := Mux(state === s_probe_rep, way_oh, ~UFix(0, NWAYS))
io.meta_req.bits.rw := state === s_probe_rep
io.meta_req.bits.idx := req.addr
io.meta_req.bits.data.state := co.newStateOnProbeRequest(req, line_state)
io.meta_req.bits.data.state := conf.co.newStateOnProbeRequest(req, line_state)
io.meta_req.bits.data.tag := req.addr >> UFix(IDX_BITS)
io.mshr_req.valid := state === s_meta_resp || state === s_mshr_req
io.addr := req.addr
@ -548,7 +548,7 @@ class ProbeUnit(co: CoherencePolicy) extends Component {
io.wb_req.bits.tag := req.addr >> UFix(IDX_BITS)
}
class FlushUnit(lines: Int, co: CoherencePolicy) extends Component {
class FlushUnit(lines: Int)(implicit conf: Configuration) extends Component {
val io = new Bundle {
val req = (new FIFOIO) { Bool() }.flip
val meta_req = (new FIFOIO) { new MetaArrayReq() }
@ -593,7 +593,7 @@ class FlushUnit(lines: Int, co: CoherencePolicy) extends Component {
io.meta_req.bits.way_en := UFixToOH(way_cnt, NWAYS)
io.meta_req.bits.idx := idx_cnt
io.meta_req.bits.rw := (state === s_reset)
io.meta_req.bits.data.state := co.newStateOnFlush()
io.meta_req.bits.data.state := conf.co.newStateOnFlush()
io.meta_req.bits.data.tag := UFix(0)
}
@ -748,7 +748,7 @@ class ioHellaCache extends Bundle {
val xcpt = (new HellaCacheExceptions).asInput
}
class HellaCache(co: CoherencePolicy) extends Component {
class HellaCache()(implicit conf: Configuration) extends Component {
val io = new Bundle {
val cpu = (new ioHellaCache).flip
val mem = new ioTileLink
@ -801,10 +801,10 @@ class HellaCache(co: CoherencePolicy) extends Component {
val r_req_readwrite = r_req_read || r_req_write || r_req_prefetch
val nack_hit = Bool()
val wb = new WritebackUnit(co)
val prober = new ProbeUnit(co)
val mshr = new MSHRFile(co)
val flusher = new FlushUnit(lines, co)
val wb = new WritebackUnit
val prober = new ProbeUnit
val mshr = new MSHRFile
val flusher = new FlushUnit(lines)
val replay_amo_val = mshr.io.data_req.valid && mshr.io.data_req.bits.cmd(3).toBool
// reset and flush unit
@ -863,10 +863,10 @@ class HellaCache(co: CoherencePolicy) extends Component {
val early_tag_nack = !meta_arb.io.in(3).ready
val cpu_req_ppn = Mux(prober.io.mshr_req.valid, prober.io.addr >> UFix(PGIDX_BITS-OFFSET_BITS), io.cpu.req.bits.ppn)
val cpu_req_tag = Cat(cpu_req_ppn, r_cpu_req_idx)(tagmsb,taglsb)
val tag_match_arr = (0 until NWAYS).map( w => co.isValid(meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag))
val tag_match_arr = (0 until NWAYS).map( w => conf.co.isValid(meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag))
val tag_match = Cat(Bits(0),tag_match_arr:_*).orR
val tag_match_way_oh = Cat(Bits(0),tag_match_arr.reverse:_*)(NWAYS-1, 0) //TODO: use Vec
val tag_hit_arr = (0 until NWAYS).map( w => co.isHit(r_cpu_req_cmd, meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag))
val tag_hit_arr = (0 until NWAYS).map( w => conf.co.isHit(r_cpu_req_cmd, meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag))
val tag_hit = Cat(Bits(0),tag_hit_arr:_*).orR
val meta_resp_way_oh = Mux(meta.io.way_en === ~UFix(0, NWAYS), tag_match_way_oh, meta.io.way_en)
val data_resp_way_oh = Mux(data.io.way_en === ~UFix(0, NWAYS), tag_match_way_oh, data.io.way_en)
@ -892,7 +892,7 @@ class HellaCache(co: CoherencePolicy) extends Component {
data_arb.io.in(0).bits.wmask := ~UFix(0, MEM_DATA_BITS/8)
data_arb.io.in(0).bits.data := io.mem.xact_rep.bits.data
data_arb.io.in(0).bits.way_en := mshr.io.mem_resp_way_oh
data_arb.io.in(0).valid := io.mem.xact_rep.valid && co.messageUpdatesDataArray(io.mem.xact_rep.bits)
data_arb.io.in(0).valid := io.mem.xact_rep.valid && conf.co.messageUpdatesDataArray(io.mem.xact_rep.bits)
// load hits
data_arb.io.in(4).bits.offset := io.cpu.req.bits.idx(offsetmsb,ramindexlsb)
@ -922,7 +922,7 @@ class HellaCache(co: CoherencePolicy) extends Component {
p_store_valid := p_store_valid && !drain_store || (r_cpu_req_val && tag_hit && r_req_store && mshr.io.req.ready && !nack_hit) || p_amo
// tag update after a store to an exclusive clean line.
val new_hit_state = co.newStateOnHit(r_cpu_req_cmd, meta_resp_mux.state)
val new_hit_state = conf.co.newStateOnHit(r_cpu_req_cmd, meta_resp_mux.state)
val set_hit_state = r_cpu_req_val && tag_hit && meta_resp_mux.state != new_hit_state
meta.io.state_req.bits.rw := Bool(true)
meta.io.state_req.bits.idx := Reg(r_cpu_req_idx(indexmsb,indexlsb))
@ -946,7 +946,7 @@ class HellaCache(co: CoherencePolicy) extends Component {
// miss handling
mshr.io.req.valid := r_cpu_req_val && r_req_readwrite && !nack_hit || flusher.io.mshr_req.valid
mshr.io.req.bits.tag_miss := !tag_hit || flusher.io.mshr_req.valid
mshr.io.req.bits.old_dirty := co.needsWriteback(meta_wb_mux.state) && (!tag_match || flusher.io.mshr_req.valid) // don't wb upgrades
mshr.io.req.bits.old_dirty := conf.co.needsWriteback(meta_wb_mux.state) && (!tag_match || flusher.io.mshr_req.valid) // don't wb upgrades
mshr.io.req.bits.old_tag := meta_wb_mux.tag
mshr.io.req.bits.tag := cpu_req_tag
mshr.io.req.bits.idx := r_cpu_req_idx(indexmsb,indexlsb)