riscv/rocket-chip
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first pass at configuration object passed as implicit parameter

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This commit is contained in:
Henry Cook
2012-10-07 22:37:29 -07:00
parent dfdfddebe8
commit 9025d0610c
8 changed files with 57 additions and 55 deletions
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4
rocket/src/main/scala/icache.scala
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@ -28,7 +28,7 @@ class ioRocketICache extends Bundle()
// 32 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines
// parameters :
// lines = # cache lines
class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) extends Component
class rocketICache(sets: Int, assoc: Int)(implicit conf: Configuration) extends Component
{
val io = new ioRocketICache();
@ -137,7 +137,7 @@ class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) exten
rdy := !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || tag_hit);
io.cpu.resp_data := data_mux.io.out
io.mem.xact_init.valid := (state === s_request) && finish_q.io.enq.ready
io.mem.xact_init.bits := co.getUncachedReadTransactionInit(r_cpu_miss_addr(tagmsb,indexlsb).toUFix, UFix(0))
io.mem.xact_init.bits := conf.co.getUncachedReadTransactionInit(r_cpu_miss_addr(tagmsb,indexlsb).toUFix, UFix(0))
io.mem.xact_finish <> finish_q.io.deq
// control state machine