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Avoid floating-point arithmetic where integers suffice

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This commit is contained in:
Andrew Waterman 2016-06-01 21:55:46 -07:00
parent 11b3cee07a
commit 8e80d1ec80
3 changed files with 3 additions and 12 deletions
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4
uncore/src/main/scala/debug.scala
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@ -432,8 +432,8 @@ class DebugModule ()(implicit val p:cde.Parameters)
val sbRamAddrWidth = log2Up((cfg.nDebugRamBytes * 8) / sbRamDataWidth) val sbRamAddrWidth = log2Up((cfg.nDebugRamBytes * 8) / sbRamDataWidth)
val sbRamAddrOffset = log2Up(tlDataBits/8) val sbRamAddrOffset = log2Up(tlDataBits/8)
val ramDataWidth = max(dbRamDataWidth, sbRamDataWidth) val ramDataWidth = dbRamDataWidth max sbRamDataWidth
val ramAddrWidth = min(dbRamAddrWidth, sbRamAddrWidth) val ramAddrWidth = dbRamAddrWidth min sbRamAddrWidth
val ramMem = Mem(1 << ramAddrWidth , UInt(width=ramDataWidth)) val ramMem = Mem(1 << ramAddrWidth , UInt(width=ramDataWidth))
val ramAddr = Wire(UInt(width=ramAddrWidth)) val ramAddr = Wire(UInt(width=ramAddrWidth))
val ramRdData = Wire(UInt(width=ramDataWidth)) val ramRdData = Wire(UInt(width=ramDataWidth))

2
uncore/src/main/scala/ecc.scala
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@ -47,7 +47,7 @@ class ParityCode extends Code
class SECCode extends Code class SECCode extends Code
{ {
def width(k: Int) = { def width(k: Int) = {
val m = new Unsigned(k).log2 + 1 val m = log2Floor(k) + 1
k + m + (if((1 << m) < m+k+1) 1 else 0) k + m + (if((1 << m) < m+k+1) 1 else 0)
} }
def encode(x: UInt) = { def encode(x: UInt) = {

9
uncore/src/main/scala/util.scala
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@ -3,15 +3,6 @@
package uncore package uncore
import Chisel._ import Chisel._
import scala.math._
class Unsigned(x: Int) {
require(x >= 0)
def clog2: Int = { require(x > 0); ceil(log(x)/log(2)).toInt }
def log2: Int = { require(x > 0); floor(log(x)/log(2)).toInt }
def isPow2: Boolean = x > 0 && (x & (x-1)) == 0
def nextPow2: Int = if (x == 0) 1 else 1 << clog2
}
object MuxBundle { object MuxBundle {
def apply[T <: Data] (default: T, mapping: Seq[(Bool, T)]): T = { def apply[T <: Data] (default: T, mapping: Seq[(Bool, T)]): T = {