From 8e80d1ec8019095c8bd9531e241ac678152908f4 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Wed, 1 Jun 2016 21:55:46 -0700
Subject: [PATCH] Avoid floating-point arithmetic where integers suffice

---
 uncore/src/main/scala/debug.scala | 4 ++--
 uncore/src/main/scala/ecc.scala   | 2 +-
 uncore/src/main/scala/util.scala  | 9 ---------
 3 files changed, 3 insertions(+), 12 deletions(-)

diff --git a/uncore/src/main/scala/debug.scala b/uncore/src/main/scala/debug.scala
index e4f96765..df382a59 100644
--- a/uncore/src/main/scala/debug.scala
+++ b/uncore/src/main/scala/debug.scala
@@ -432,8 +432,8 @@ class DebugModule ()(implicit val p:cde.Parameters)
   val sbRamAddrWidth    = log2Up((cfg.nDebugRamBytes * 8) / sbRamDataWidth)
   val sbRamAddrOffset   = log2Up(tlDataBits/8)
 
-  val ramDataWidth = max(dbRamDataWidth, sbRamDataWidth)
-  val ramAddrWidth  = min(dbRamAddrWidth, sbRamAddrWidth)
+  val ramDataWidth = dbRamDataWidth max sbRamDataWidth
+  val ramAddrWidth  = dbRamAddrWidth min sbRamAddrWidth
   val ramMem    = Mem(1 << ramAddrWidth , UInt(width=ramDataWidth))
   val ramAddr   = Wire(UInt(width=ramAddrWidth))
   val ramRdData = Wire(UInt(width=ramDataWidth))
diff --git a/uncore/src/main/scala/ecc.scala b/uncore/src/main/scala/ecc.scala
index 3f16901c..4a582fc1 100644
--- a/uncore/src/main/scala/ecc.scala
+++ b/uncore/src/main/scala/ecc.scala
@@ -47,7 +47,7 @@ class ParityCode extends Code
 class SECCode extends Code
 {
   def width(k: Int) = {
-    val m = new Unsigned(k).log2 + 1
+    val m = log2Floor(k) + 1
     k + m + (if((1 << m) < m+k+1) 1 else 0)
   }
   def encode(x: UInt) = {
diff --git a/uncore/src/main/scala/util.scala b/uncore/src/main/scala/util.scala
index 12316458..d0afa758 100644
--- a/uncore/src/main/scala/util.scala
+++ b/uncore/src/main/scala/util.scala
@@ -3,15 +3,6 @@
 package uncore
 
 import Chisel._
-import scala.math._
-
-class Unsigned(x: Int) {
-  require(x >= 0)
-  def clog2: Int = { require(x > 0); ceil(log(x)/log(2)).toInt }
-  def log2: Int = { require(x > 0); floor(log(x)/log(2)).toInt }
-  def isPow2: Boolean = x > 0 && (x & (x-1)) == 0
-  def nextPow2: Int = if (x == 0) 1 else 1 << clog2
-}
 
 object MuxBundle {
   def apply[T <: Data] (default: T, mapping: Seq[(Bool, T)]): T = {