riscv/rocket-chip
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fix Tile reset power on behavior

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This commit is contained in:
Howard Mao 2016-06-07 11:06:25 -07:00
parent e6c4372332
commit 8db27a36c4
1 changed files with 3 additions and 1 deletions
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4
src/main/scala/RocketChip.scala
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@ -242,7 +242,9 @@ class Uncore(implicit val p: Parameters) extends Module
prci.io.interrupts(i).seip := plic.io.harts(plic.cfg.context(i, 'S'))
prci.io.interrupts(i).debug := debugModule.io.debugInterrupts(i)
io.prci(i).reset := Reg(next=Reg(next=htif.io.cpu(i).reset)) // TODO
io.prci(i).reset := reset || Reg(init = Bool(true),
next=Reg(init = Bool(true),
next=htif.io.cpu(i).reset)) // TODO
}
val bootROM = Module(new ROMSlave(TopUtils.makeBootROM()))