riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Revert "async_queue: Give names to all the registers which show up in the queue (#390)"

Browse Source 
This reverts commit a84a961a39.

The changes to RegisterCrossing.scala were unneeded after application of this branch.
The name changes made to the AsyncQueue.scala are reapplied at the end of this branch.
This commit is contained in:
Wesley W. Terpstra
2016-10-08 20:15:45 -07:00
parent b6bc6b7a4d
commit 8c7d469a95
2 changed files with 28 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
src/main/scala/regmapper/RegisterCrossing.scala
View File

@ -72,15 +72,15 @@ class RegisterWriteCrossing[T <: Data](gen: T, sync: Int = 3) extends Module {
// If the slave is not operational, just drop the write.
val progress = crossing.io.enq.ready || !io.master_allow
val control = Module(new BusyRegisterCrossing(io.master_clock, io.master_reset))
control.io.progress := progress
control.io.request_valid := io.master_port.request.valid
control.io.response_ready := io.master_port.response.ready
val reg = Module(new BusyRegisterCrossing(io.master_clock, io.master_reset))
reg.io.progress := progress
reg.io.request_valid := io.master_port.request.valid
reg.io.response_ready := io.master_port.response.ready
crossing.io.deq.ready := Bool(true)
crossing.io.enq.valid := io.master_port.request.valid && !control.io.busy
io.master_port.request.ready := progress && !control.io.busy
io.master_port.response.valid := progress && control.io.busy
crossing.io.enq.valid := io.master_port.request.valid && !reg.io.busy
io.master_port.request.ready := progress && !reg.io.busy
io.master_port.response.valid := progress && reg.io.busy
}
// RegField should support connecting to one of these
@ -121,14 +121,14 @@ class RegisterReadCrossing[T <: Data](gen: T, sync: Int = 3) extends Module {
// If the slave is not operational, just repeat the last value we saw.
val progress = crossing.io.deq.valid || !io.master_allow
val control = Module(new BusyRegisterCrossing(io.master_clock, io.master_reset))
control.io.progress := progress
control.io.request_valid := io.master_port.request.valid
control.io.response_ready := io.master_port.response.ready
val reg = Module(new BusyRegisterCrossing(io.master_clock, io.master_reset))
reg.io.progress := progress
reg.io.request_valid := io.master_port.request.valid
reg.io.response_ready := io.master_port.response.ready
io.master_port.response.valid := progress && control.io.busy
io.master_port.request.ready := progress && !control.io.busy
crossing.io.deq.ready := io.master_port.request.valid && !control.io.busy
io.master_port.response.valid := progress && reg.io.busy
io.master_port.request.ready := progress && !reg.io.busy
crossing.io.deq.ready := io.master_port.request.valid && !reg.io.busy
crossing.io.enq.valid := Bool(true)
}