Bump chisel and firrtl (#1232)

* Misc changes to better enable autoclonetype
* Bump chisel3 and firrtl and SBT to 1.1.1

chisel3

@@ -1 +1 @@
-Subproject commit e27657118ff5915b96f8e3a467d464245fe09769
+Subproject commit 97871178cb511063965f971b768f91c289c4776f

firrtl

@@ -1 +1 @@
-Subproject commit 57025111d3bc872da726e31e3e9a1e4895593266
+Subproject commit b90fc784a1819c1d7905910130a7da022214bc22

project/build.properties

@@ -1 +1 @@
-sbt.version=1.0.4
+sbt.version=1.1.1

src/main/scala/rocket/Frontend.scala

@@ -62,7 +62,7 @@ class Frontend(val icacheParams: ICacheParams, hartid: Int)(implicit p: Paramete
   val slaveNode = icache.slaveNode
 }
 
-class FrontendBundle(outer: Frontend) extends CoreBundle()(outer.p)
+class FrontendBundle(val outer: Frontend) extends CoreBundle()(outer.p)
     with HasExternallyDrivenTileConstants {
   val cpu = new FrontendIO().flip
   val ptw = new TLBPTWIO()

src/main/scala/rocket/HellaCache.scala

@@ -173,7 +173,7 @@ abstract class HellaCache(hartid: Int)(implicit p: Parameters) extends LazyModul
   val module: HellaCacheModule
 }
 
-class HellaCacheBundle(outer: HellaCache)(implicit p: Parameters) extends CoreBundle()(p) {
+class HellaCacheBundle(val outer: HellaCache)(implicit p: Parameters) extends CoreBundle()(p) {
   val hartid = UInt(INPUT, hartIdLen)
   val cpu = (new HellaCacheIO).flip
   val ptw = new TLBPTWIO()

src/main/scala/rocket/ICache.scala

@@ -81,7 +81,7 @@ class ICachePerfEvents extends Bundle {
   val acquire = Bool()
 }
 
-class ICacheBundle(outer: ICache) extends CoreBundle()(outer.p) {
+class ICacheBundle(val outer: ICache) extends CoreBundle()(outer.p) {
   val hartid = UInt(INPUT, hartIdLen)
   val req = Decoupled(new ICacheReq).flip
   val s1_paddr = UInt(INPUT, paddrBits) // delayed one cycle w.r.t. req

src/main/scala/tilelink/RegisterRouter.scala

@@ -143,7 +143,7 @@ class TLRegBundleBase(arg: TLRegBundleArg) extends Bundle
   implicit val p = arg.p
 }
 
-class TLRegBundle[P](val params: P, arg: TLRegBundleArg)(implicit p: Parameters) extends TLRegBundleBase(arg)
+class TLRegBundle[P](val params: P, val arg: TLRegBundleArg) extends TLRegBundleBase(arg)
 
 class TLRegModule[P, B <: TLRegBundleBase](val params: P, bundleBuilder: => B, router: TLRegisterRouterBase)
   extends LazyModuleImp(router) with HasRegMap

src/main/scala/util/HeterogeneousBag.scala

@@ -11,7 +11,7 @@ final case class HeterogeneousBag[T <: Data](elts: Seq[T]) extends Record with c
   def length = elts.length
 
   val elements = ListMap(elts.zipWithIndex.map { case (n,i) => (i.toString, n) }:_*)
-  override def cloneType: this.type = (new HeterogeneousBag(elts.map(_.cloneType))).asInstanceOf[this.type]
+  override def cloneType: this.type = (new HeterogeneousBag(elts.map(_.chiselCloneType))).asInstanceOf[this.type]
 
   // IndexedSeq has its own hashCode/equals that we must not use
   override def hashCode: Int = super[Record].hashCode

src/main/scala/util/Misc.scala

@@ -8,19 +8,7 @@ import chisel3.experimental.{ChiselAnnotation, RawModule}
 import freechips.rocketchip.config.Parameters
 import scala.math._
 
-class ParameterizedBundle(implicit p: Parameters) extends Bundle {
+class ParameterizedBundle(implicit p: Parameters) extends Bundle
-  override def cloneType = {
-    try {
-      this.getClass.getConstructors.head.newInstance(p).asInstanceOf[this.type]
-    } catch {
-      case e: java.lang.IllegalArgumentException =>
-        throwException("Unable to use ParamaterizedBundle.cloneType on " +
-                       this.getClass + ", probably because " + this.getClass +
-                       "() takes more than one argument.  Consider overriding " +
-                       "cloneType() on " + this.getClass, e)
-    }
-  }
-}
 
 // TODO: replace this with an implicit class when @chisel unprotects dontTouchPorts
 trait DontTouch {
@@ -101,7 +89,7 @@ object ValidMux {
     apply(v1 +: v2.toSeq)
   }
   def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
-    val out = Wire(Valid(valids.head.bits))
+    val out = Wire(Valid(valids.head.bits.cloneType))
     out.valid := valids.map(_.valid).reduce(_ || _)
     out.bits := MuxCase(valids.head.bits,
       valids.map(v => (v.valid -> v.bits)))