443 lines
19 KiB
Scala
443 lines
19 KiB
Scala
// See LICENSE.Berkeley for license details.
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.rocket
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import Chisel._
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import Chisel.ImplicitConversions._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.subsystem.RocketTilesKey
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tile._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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import freechips.rocketchip.util.property._
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import chisel3.internal.sourceinfo.SourceInfo
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case class ICacheParams(
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nSets: Int = 64,
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nWays: Int = 4,
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rowBits: Int = 128,
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nTLBEntries: Int = 32,
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cacheIdBits: Int = 0,
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tagECC: Code = new IdentityCode,
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dataECC: Code = new IdentityCode,
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itimAddr: Option[BigInt] = None,
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prefetch: Boolean = false,
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blockBytes: Int = 64,
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latency: Int = 2,
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fetchBytes: Int = 4) extends L1CacheParams {
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def replacement = new RandomReplacement(nWays)
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}
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trait HasL1ICacheParameters extends HasL1CacheParameters with HasCoreParameters {
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val cacheParams = tileParams.icache.get
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}
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class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICacheParameters {
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val addr = UInt(width = vaddrBits)
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}
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class ICacheErrors(implicit p: Parameters) extends CoreBundle()(p)
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with HasL1ICacheParameters
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with CanHaveErrors {
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val correctable = (cacheParams.tagECC.canDetect || cacheParams.dataECC.canDetect).option(Valid(UInt(width = paddrBits)))
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val uncorrectable = (cacheParams.itimAddr.nonEmpty && cacheParams.dataECC.canDetect).option(Valid(UInt(width = paddrBits)))
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}
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class ICache(val icacheParams: ICacheParams, val hartId: Int)(implicit p: Parameters) extends LazyModule {
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lazy val module = new ICacheModule(this)
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val masterNode = TLClientNode(Seq(TLClientPortParameters(Seq(TLClientParameters(
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sourceId = IdRange(0, 1 + icacheParams.prefetch.toInt), // 0=refill, 1=hint
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name = s"Core ${hartId} ICache")))))
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val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes
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val device = new SimpleDevice("itim", Seq("sifive,itim0"))
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private val wordBytes = icacheParams.fetchBytes
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val slaveNode =
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TLManagerNode(icacheParams.itimAddr.toSeq.map { itimAddr => TLManagerPortParameters(
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Seq(TLManagerParameters(
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address = Seq(AddressSet(itimAddr, size-1)),
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resources = device.reg("mem"),
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regionType = RegionType.UNCACHEABLE,
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executable = true,
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supportsPutFull = TransferSizes(1, wordBytes),
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supportsPutPartial = TransferSizes(1, wordBytes),
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supportsGet = TransferSizes(1, wordBytes),
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fifoId = Some(0))), // requests handled in FIFO order
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beatBytes = wordBytes,
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minLatency = 1)})
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}
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class ICacheResp(outer: ICache) extends Bundle {
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val data = UInt(width = outer.icacheParams.fetchBytes*8)
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val replay = Bool()
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val ae = Bool()
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override def cloneType = new ICacheResp(outer).asInstanceOf[this.type]
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}
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class ICachePerfEvents extends Bundle {
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val acquire = Bool()
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}
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class ICacheBundle(val outer: ICache) extends CoreBundle()(outer.p) {
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val hartid = UInt(INPUT, hartIdLen)
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val req = Decoupled(new ICacheReq).flip
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val s1_paddr = UInt(INPUT, paddrBits) // delayed one cycle w.r.t. req
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val s2_vaddr = UInt(INPUT, vaddrBits) // delayed two cycles w.r.t. req
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val s1_kill = Bool(INPUT) // delayed one cycle w.r.t. req
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val s2_kill = Bool(INPUT) // delayed two cycles; prevents I$ miss emission
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val s2_prefetch = Bool(INPUT) // should I$ prefetch next line on a miss?
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val resp = Valid(new ICacheResp(outer))
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val invalidate = Bool(INPUT)
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val errors = new ICacheErrors
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val perf = new ICachePerfEvents().asOutput
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}
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// get a tile-specific property without breaking deduplication
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object GetPropertyByHartId {
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def apply[T <: Data](tiles: Seq[RocketTileParams], f: RocketTileParams => Option[T], hartId: UInt): T = {
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PriorityMux(tiles.collect { case t if f(t).isDefined => (t.hartId === hartId) -> f(t).get })
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}
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}
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class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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with HasL1ICacheParameters {
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override val cacheParams = outer.icacheParams // Use the local parameters
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val io = IO(new ICacheBundle(outer))
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val (tl_out, edge_out) = outer.masterNode.out(0)
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// Option.unzip does not exist :-(
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val (tl_in, edge_in) = outer.slaveNode.in.headOption.unzip
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val tECC = cacheParams.tagECC
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val dECC = cacheParams.dataECC
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require(isPow2(nSets) && isPow2(nWays))
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require(!usingVM || pgIdxBits >= untagBits)
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val scratchpadOn = RegInit(false.B)
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val scratchpadMax = tl_in.map(tl => Reg(UInt(width = log2Ceil(nSets * (nWays - 1)))))
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def lineInScratchpad(line: UInt) = scratchpadMax.map(scratchpadOn && line <= _).getOrElse(false.B)
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val scratchpadBase = outer.icacheParams.itimAddr.map { dummy =>
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GetPropertyByHartId(p(RocketTilesKey), _.icache.flatMap(_.itimAddr.map(_.U)), io.hartid)
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}
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def addrMaybeInScratchpad(addr: UInt) = scratchpadBase.map(base => addr >= base && addr < base + outer.size).getOrElse(false.B)
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def addrInScratchpad(addr: UInt) = addrMaybeInScratchpad(addr) && lineInScratchpad(addr(untagBits+log2Ceil(nWays)-1, blockOffBits))
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def scratchpadWay(addr: UInt) = addr.extract(untagBits+log2Ceil(nWays)-1, untagBits)
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def scratchpadWayValid(way: UInt) = way < nWays - 1
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def scratchpadLine(addr: UInt) = addr(untagBits+log2Ceil(nWays)-1, blockOffBits)
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val s0_slaveValid = tl_in.map(_.a.fire()).getOrElse(false.B)
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val s1_slaveValid = RegNext(s0_slaveValid, false.B)
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val s2_slaveValid = RegNext(s1_slaveValid, false.B)
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val s3_slaveValid = RegNext(false.B)
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val s1_valid = Reg(init=Bool(false))
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val s1_tag_hit = Wire(Vec(nWays, Bool()))
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val s1_hit = s1_tag_hit.reduce(_||_) || Mux(s1_slaveValid, true.B, addrMaybeInScratchpad(io.s1_paddr))
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val s2_valid = RegNext(s1_valid && !io.s1_kill, Bool(false))
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val s2_hit = RegNext(s1_hit)
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val invalidated = Reg(Bool())
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val refill_valid = RegInit(false.B)
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val send_hint = RegInit(false.B)
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val refill_fire = tl_out.a.fire() && !send_hint
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val hint_outstanding = RegInit(false.B)
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val s2_miss = s2_valid && !s2_hit && !io.s2_kill && !RegNext(refill_valid)
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val refill_addr = RegEnable(io.s1_paddr, s1_valid && !(refill_valid || s2_miss))
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val refill_tag = refill_addr(tagBits+untagBits-1,untagBits)
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val refill_idx = refill_addr(untagBits-1,blockOffBits)
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val refill_one_beat = tl_out.d.fire() && edge_out.hasData(tl_out.d.bits)
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io.req.ready := !(refill_one_beat || s0_slaveValid || s3_slaveValid)
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val s0_valid = io.req.fire()
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val s0_vaddr = io.req.bits.addr
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s1_valid := s0_valid
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val (_, _, d_done, refill_cnt) = edge_out.count(tl_out.d)
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val refill_done = refill_one_beat && d_done
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tl_out.d.ready := !s3_slaveValid
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require (edge_out.manager.minLatency > 0)
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val repl_way = if (isDM) UInt(0) else {
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// pick a way that is not used by the scratchpad
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val v0 = LFSR16(refill_fire)(log2Up(nWays)-1,0)
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var v = v0
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for (i <- log2Ceil(nWays) - 1 to 0 by -1) {
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val mask = nWays - (BigInt(1) << (i + 1))
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v = v | (lineInScratchpad(Cat(v0 | mask.U, refill_idx)) << i)
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}
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assert(!lineInScratchpad(Cat(v, refill_idx)))
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v
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}
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val tag_array = SeqMem(nSets, Vec(nWays, UInt(width = tECC.width(1 + tagBits))))
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val tag_rdata = tag_array.read(s0_vaddr(untagBits-1,blockOffBits), !refill_done && s0_valid)
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val accruedRefillError = Reg(Bool())
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when (refill_done) {
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val enc_tag = tECC.encode(Cat(tl_out.d.bits.error, refill_tag))
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tag_array.write(refill_idx, Vec.fill(nWays)(enc_tag), Seq.tabulate(nWays)(repl_way === _))
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ccover(tl_out.d.bits.error, "D_ERROR", "I$ D-channel error")
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}
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val vb_array = Reg(init=Bits(0, nSets*nWays))
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when (refill_one_beat) {
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// clear bit when refill starts so hit-under-miss doesn't fetch bad data
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vb_array := vb_array.bitSet(Cat(repl_way, refill_idx), refill_done && !invalidated)
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}
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val invalidate = Wire(init = io.invalidate)
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when (invalidate) {
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vb_array := Bits(0)
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invalidated := Bool(true)
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}
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val s1_tag_disparity = Wire(Vec(nWays, Bool()))
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val s1_tl_error = Wire(Vec(nWays, Bool()))
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val wordBits = outer.icacheParams.fetchBytes*8
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val s1_dout = Wire(Vec(nWays, UInt(width = dECC.width(wordBits))))
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val s0_slaveAddr = tl_in.map(_.a.bits.address).getOrElse(0.U)
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val s1s3_slaveAddr = Reg(UInt(width = log2Ceil(outer.size)))
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val s1s3_slaveData = Reg(UInt(width = wordBits))
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for (i <- 0 until nWays) {
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val s1_idx = io.s1_paddr(untagBits-1,blockOffBits)
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val s1_tag = io.s1_paddr(tagBits+untagBits-1,untagBits)
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val scratchpadHit = scratchpadWayValid(i) &&
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Mux(s1_slaveValid,
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lineInScratchpad(scratchpadLine(s1s3_slaveAddr)) && scratchpadWay(s1s3_slaveAddr) === i,
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addrInScratchpad(io.s1_paddr) && scratchpadWay(io.s1_paddr) === i)
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val s1_vb = vb_array(Cat(UInt(i), s1_idx)) && !s1_slaveValid
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val enc_tag = tECC.decode(tag_rdata(i))
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val (tl_error, tag) = Split(enc_tag.uncorrected, tagBits)
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val tagMatch = s1_vb && tag === s1_tag
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s1_tag_disparity(i) := s1_vb && enc_tag.error
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s1_tl_error(i) := tagMatch && tl_error.toBool
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s1_tag_hit(i) := tagMatch || scratchpadHit
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}
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assert(!(s1_valid || s1_slaveValid) || PopCount(s1_tag_hit zip s1_tag_disparity map { case (h, d) => h && !d }) <= 1)
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require(tl_out.d.bits.data.getWidth % wordBits == 0)
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val data_arrays = Seq.fill(tl_out.d.bits.data.getWidth / wordBits) { SeqMem(nSets * refillCycles, Vec(nWays, UInt(width = dECC.width(wordBits)))) }
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for ((data_array, i) <- data_arrays zipWithIndex) {
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def wordMatch(addr: UInt) = addr.extract(log2Ceil(tl_out.d.bits.data.getWidth/8)-1, log2Ceil(wordBits/8)) === i
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def row(addr: UInt) = addr(untagBits-1, blockOffBits-log2Ceil(refillCycles))
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val s0_ren = (s0_valid && wordMatch(s0_vaddr)) || (s0_slaveValid && wordMatch(s0_slaveAddr))
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val wen = (refill_one_beat && !invalidated) || (s3_slaveValid && wordMatch(s1s3_slaveAddr))
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val mem_idx = Mux(refill_one_beat, (refill_idx << log2Ceil(refillCycles)) | refill_cnt,
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Mux(s3_slaveValid, row(s1s3_slaveAddr),
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Mux(s0_slaveValid, row(s0_slaveAddr),
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row(s0_vaddr))))
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when (wen) {
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val data = Mux(s3_slaveValid, s1s3_slaveData, tl_out.d.bits.data(wordBits*(i+1)-1, wordBits*i))
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val way = Mux(s3_slaveValid, scratchpadWay(s1s3_slaveAddr), repl_way)
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data_array.write(mem_idx, Vec.fill(nWays)(dECC.encode(data)), (0 until nWays).map(way === _))
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}
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val dout = data_array.read(mem_idx, !wen && s0_ren)
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when (wordMatch(Mux(s1_slaveValid, s1s3_slaveAddr, io.s1_paddr))) {
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s1_dout := dout
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}
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}
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val s1_clk_en = s1_valid || s1_slaveValid
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val s2_tag_hit = RegEnable(s1_tag_hit, s1_clk_en)
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val s2_hit_way = OHToUInt(s2_tag_hit)
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val s2_scratchpad_word_addr = Cat(s2_hit_way, Mux(s2_slaveValid, s1s3_slaveAddr, io.s2_vaddr)(untagBits-1, log2Ceil(wordBits/8)), UInt(0, log2Ceil(wordBits/8)))
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val s2_dout = RegEnable(s1_dout, s1_clk_en)
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val s2_way_mux = Mux1H(s2_tag_hit, s2_dout)
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val s2_tag_disparity = RegEnable(s1_tag_disparity, s1_clk_en).asUInt.orR
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val s2_tl_error = RegEnable(s1_tl_error.asUInt.orR, s1_clk_en)
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val s2_data_decoded = dECC.decode(s2_way_mux)
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val s2_disparity = s2_tag_disparity || s2_data_decoded.error
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val s2_full_word_write = Wire(init = false.B)
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val s1_scratchpad_hit = Mux(s1_slaveValid, lineInScratchpad(scratchpadLine(s1s3_slaveAddr)), addrInScratchpad(io.s1_paddr))
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val s2_scratchpad_hit = RegEnable(s1_scratchpad_hit, s1_clk_en)
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val s2_report_uncorrectable_error = s2_scratchpad_hit && s2_data_decoded.uncorrectable && (s2_valid || (s2_slaveValid && !s2_full_word_write))
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val s2_error_addr = scratchpadBase.map(base => Mux(s2_scratchpad_hit, base + s2_scratchpad_word_addr, 0.U)).getOrElse(0.U)
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// output signals
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outer.icacheParams.latency match {
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case 1 =>
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require(tECC.isInstanceOf[IdentityCode])
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require(dECC.isInstanceOf[IdentityCode])
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require(outer.icacheParams.itimAddr.isEmpty)
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io.resp.bits.data := Mux1H(s1_tag_hit, s1_dout)
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io.resp.bits.ae := s1_tl_error.asUInt.orR
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io.resp.valid := s1_valid && s1_hit
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case 2 =>
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// when some sort of memory bit error have occurred
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when (s2_valid && s2_disparity) { invalidate := true }
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io.resp.bits.data := s2_data_decoded.uncorrected
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io.resp.bits.ae := s2_tl_error
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io.resp.bits.replay := s2_disparity
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io.resp.valid := s2_valid && s2_hit
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io.errors.correctable.foreach { c =>
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c.valid := (s2_valid || s2_slaveValid) && s2_disparity && !s2_report_uncorrectable_error
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c.bits := s2_error_addr
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}
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io.errors.uncorrectable.foreach { u =>
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u.valid := s2_report_uncorrectable_error
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u.bits := s2_error_addr
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}
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tl_in.map { tl =>
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val respValid = RegInit(false.B)
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tl.a.ready := !(tl_out.d.valid || s1_slaveValid || s2_slaveValid || s3_slaveValid || respValid)
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val s1_a = RegEnable(tl.a.bits, s0_slaveValid)
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s2_full_word_write := edge_in.get.hasData(s1_a) && s1_a.mask.andR
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when (s0_slaveValid) {
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val a = tl.a.bits
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s1s3_slaveAddr := tl.a.bits.address
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s1s3_slaveData := tl.a.bits.data
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when (edge_in.get.hasData(a)) {
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val enable = scratchpadWayValid(scratchpadWay(a.address))
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when (!lineInScratchpad(scratchpadLine(a.address))) {
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scratchpadMax.get := scratchpadLine(a.address)
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invalidate := true
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}
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scratchpadOn := enable
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val itim_allocated = !scratchpadOn && enable
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val itim_deallocated = scratchpadOn && !enable
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val itim_increase = scratchpadOn && enable && scratchpadLine(a.address) > scratchpadMax.get
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val refilling = refill_valid && refill_cnt > 0
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ccover(itim_allocated, "ITIM_ALLOCATE", "ITIM allocated")
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ccover(itim_allocated && refilling, "ITIM_ALLOCATE_WHILE_REFILL", "ITIM allocated while I$ refill")
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ccover(itim_deallocated, "ITIM_DEALLOCATE", "ITIM deallocated")
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ccover(itim_deallocated && refilling, "ITIM_DEALLOCATE_WHILE_REFILL", "ITIM deallocated while I$ refill")
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ccover(itim_increase, "ITIM_SIZE_INCREASE", "ITIM size increased")
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ccover(itim_increase && refilling, "ITIM_SIZE_INCREASE_WHILE_REFILL", "ITIM size increased while I$ refill")
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}
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}
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assert(!s2_valid || RegNext(RegNext(s0_vaddr)) === io.s2_vaddr)
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when (!(tl.a.valid || s1_slaveValid || s2_slaveValid || respValid)
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&& s2_valid && s2_data_decoded.error && !s2_tag_disparity) {
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// handle correctable errors on CPU accesses to the scratchpad.
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// if there is an in-flight slave-port access to the scratchpad,
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// report the a miss but don't correct the error (as there is
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// a structural hazard on s1s3_slaveData/s1s3_slaveAddress).
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s3_slaveValid := true
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s1s3_slaveData := s2_data_decoded.corrected
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s1s3_slaveAddr := s2_scratchpad_word_addr | s1s3_slaveAddr(log2Ceil(wordBits/8)-1, 0)
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}
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respValid := s2_slaveValid || (respValid && !tl.d.ready)
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val respError = RegEnable(s2_scratchpad_hit && s2_data_decoded.uncorrectable && !s2_full_word_write, s2_slaveValid)
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when (s2_slaveValid) {
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when (edge_in.get.hasData(s1_a) || s2_data_decoded.error) { s3_slaveValid := true }
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def byteEn(i: Int) = !(edge_in.get.hasData(s1_a) && s1_a.mask(i))
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s1s3_slaveData := (0 until wordBits/8).map(i => Mux(byteEn(i), s2_data_decoded.corrected, s1s3_slaveData)(8*(i+1)-1, 8*i)).asUInt
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}
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tl.d.valid := respValid
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tl.d.bits := Mux(edge_in.get.hasData(s1_a),
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edge_in.get.AccessAck(s1_a),
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edge_in.get.AccessAck(s1_a, UInt(0)))
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tl.d.bits.data := s1s3_slaveData
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tl.d.bits.error := respError
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// Tie off unused channels
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tl.b.valid := false
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|
tl.c.ready := true
|
|
tl.e.ready := true
|
|
|
|
ccover(s0_valid && s1_slaveValid, "CONCURRENT_ITIM_ACCESS_1", "ITIM accessed, then I$ accessed next cycle")
|
|
ccover(s0_valid && s2_slaveValid, "CONCURRENT_ITIM_ACCESS_2", "ITIM accessed, then I$ accessed two cycles later")
|
|
ccover(tl.d.valid && !tl.d.ready, "ITIM_D_STALL", "ITIM response blocked by D-channel")
|
|
ccover(tl_out.d.valid && !tl_out.d.ready, "ITIM_BLOCK_D", "D-channel blocked by ITIM access")
|
|
}
|
|
}
|
|
|
|
tl_out.a.valid := s2_miss && !refill_valid
|
|
tl_out.a.bits := edge_out.Get(
|
|
fromSource = UInt(0),
|
|
toAddress = (refill_addr >> blockOffBits) << blockOffBits,
|
|
lgSize = lgCacheBlockBytes)._2
|
|
if (cacheParams.prefetch) {
|
|
val (crosses_page, next_block) = Split(refill_addr(pgIdxBits-1, blockOffBits) +& 1, pgIdxBits-blockOffBits)
|
|
when (tl_out.a.fire()) {
|
|
send_hint := !hint_outstanding && io.s2_prefetch && !crosses_page
|
|
when (send_hint) {
|
|
send_hint := false
|
|
hint_outstanding := true
|
|
}
|
|
}
|
|
when (refill_done) {
|
|
send_hint := false
|
|
}
|
|
when (tl_out.d.fire() && !refill_one_beat) {
|
|
hint_outstanding := false
|
|
}
|
|
|
|
when (send_hint) {
|
|
tl_out.a.valid := true
|
|
tl_out.a.bits := edge_out.Hint(
|
|
fromSource = UInt(1),
|
|
toAddress = Cat(refill_addr >> pgIdxBits, next_block) << blockOffBits,
|
|
lgSize = lgCacheBlockBytes,
|
|
param = TLHints.PREFETCH_READ)._2
|
|
}
|
|
|
|
ccover(send_hint && !tl_out.a.ready, "PREFETCH_A_STALL", "I$ prefetch blocked by A-channel")
|
|
ccover(refill_valid && (tl_out.d.fire() && !refill_one_beat), "PREFETCH_D_BEFORE_MISS_D", "I$ prefetch resolves before miss")
|
|
ccover(!refill_valid && (tl_out.d.fire() && !refill_one_beat), "PREFETCH_D_AFTER_MISS_D", "I$ prefetch resolves after miss")
|
|
ccover(tl_out.a.fire() && hint_outstanding, "PREFETCH_D_AFTER_MISS_A", "I$ prefetch resolves after second miss")
|
|
}
|
|
tl_out.b.ready := Bool(true)
|
|
tl_out.c.valid := Bool(false)
|
|
tl_out.e.valid := Bool(false)
|
|
assert(!(tl_out.a.valid && addrMaybeInScratchpad(tl_out.a.bits.address)))
|
|
|
|
when (!refill_valid) { invalidated := false.B }
|
|
when (refill_fire) { refill_valid := true.B }
|
|
when (refill_done) { refill_valid := false.B}
|
|
|
|
io.perf.acquire := refill_fire
|
|
|
|
ccover(!send_hint && (tl_out.a.valid && !tl_out.a.ready), "MISS_A_STALL", "I$ miss blocked by A-channel")
|
|
ccover(invalidate && refill_valid, "FLUSH_DURING_MISS", "I$ flushed during miss")
|
|
|
|
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
|
|
cover(cond, s"ICACHE_$label", "MemorySystem;;" + desc)
|
|
|
|
val mem_active_valid = Seq(CoverBoolean(s2_valid, Seq("mem_active")))
|
|
val data_error = Seq(
|
|
CoverBoolean(!s2_data_decoded.correctable && !s2_data_decoded.uncorrectable, Seq("no_data_error")),
|
|
CoverBoolean(s2_data_decoded.correctable, Seq("data_correctable_error")),
|
|
CoverBoolean(s2_data_decoded.uncorrectable, Seq("data_uncorrectable_error")))
|
|
val request_source = Seq(
|
|
CoverBoolean(!s2_slaveValid, Seq("from_CPU")),
|
|
CoverBoolean(s2_slaveValid, Seq("from_TL"))
|
|
)
|
|
val tag_error = Seq(
|
|
CoverBoolean(!s2_tag_disparity, Seq("no_tag_error")),
|
|
CoverBoolean(s2_tag_disparity, Seq("tag_error"))
|
|
)
|
|
val mem_mode = Seq(
|
|
CoverBoolean(s2_scratchpad_hit, Seq("ITIM_mode")),
|
|
CoverBoolean(!s2_scratchpad_hit, Seq("cache_mode"))
|
|
)
|
|
|
|
val error_cross_covers = new CrossProperty(
|
|
Seq(mem_active_valid, data_error, tag_error, request_source, mem_mode),
|
|
Seq(
|
|
// tag error cannot occur in ITIM mode
|
|
Seq("tag_error", "ITIM_mode"),
|
|
// Can only respond to TL in ITIM mode
|
|
Seq("from_TL", "cache_mode")
|
|
),
|
|
"MemorySystem;;Memory Bit Flip Cross Covers")
|
|
|
|
cover(error_cross_covers)
|
|
}
|