322 lines
13 KiB
Scala
322 lines
13 KiB
Scala
// See LICENSE.Berkeley for license details.
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.rocket
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import Chisel._
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import Chisel.ImplicitConversions._
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import chisel3.core.withReset
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import freechips.rocketchip.config._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.tile._
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import freechips.rocketchip.util._
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import freechips.rocketchip.util.property._
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import chisel3.internal.sourceinfo.SourceInfo
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class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) {
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val pc = UInt(width = vaddrBitsExtended)
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val speculative = Bool()
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}
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class FrontendExceptions extends Bundle {
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val pf = new Bundle {
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val inst = Bool()
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}
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val ae = new Bundle {
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val inst = Bool()
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}
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}
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class FrontendResp(implicit p: Parameters) extends CoreBundle()(p) {
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val btb = new BTBResp
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val pc = UInt(width = vaddrBitsExtended) // ID stage PC
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val data = UInt(width = fetchWidth * coreInstBits)
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val mask = Bits(width = fetchWidth)
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val xcpt = new FrontendExceptions
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val replay = Bool()
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}
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class FrontendPerfEvents extends Bundle {
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val acquire = Bool()
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val tlbMiss = Bool()
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}
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class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
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val req = Valid(new FrontendReq)
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val sfence = Valid(new SFenceReq)
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val resp = Decoupled(new FrontendResp).flip
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val btb_update = Valid(new BTBUpdate)
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val bht_update = Valid(new BHTUpdate)
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val ras_update = Valid(new RASUpdate)
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val flush_icache = Bool(OUTPUT)
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val npc = UInt(INPUT, width = vaddrBitsExtended)
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val perf = new FrontendPerfEvents().asInput
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}
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class Frontend(val icacheParams: ICacheParams, hartid: Int)(implicit p: Parameters) extends LazyModule {
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lazy val module = new FrontendModule(this)
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val icache = LazyModule(new ICache(icacheParams, hartid))
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val masterNode = icache.masterNode
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val slaveNode = icache.slaveNode
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}
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class FrontendBundle(val outer: Frontend) extends CoreBundle()(outer.p)
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with HasExternallyDrivenTileConstants {
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val cpu = new FrontendIO().flip
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val ptw = new TLBPTWIO()
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val errors = new ICacheErrors
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}
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class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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with HasCoreParameters
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with HasL1ICacheParameters {
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val io = IO(new FrontendBundle(outer))
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implicit val edge = outer.masterNode.edges.out(0)
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val icache = outer.icache.module
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require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes)
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val tlb = Module(new TLB(true, log2Ceil(fetchBytes), nTLBEntries))
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val fq = withReset(reset || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 5, flow = true)) }
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val s0_valid = io.cpu.req.valid || !fq.io.mask(fq.io.mask.getWidth-3)
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val s1_valid = RegNext(s0_valid)
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val s1_pc = Reg(UInt(width=vaddrBitsExtended))
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val s1_speculative = Reg(Bool())
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val s2_valid = RegInit(false.B)
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val s2_pc = RegInit(t = UInt(width = vaddrBitsExtended), alignPC(io.reset_vector))
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val s2_btb_resp_valid = if (usingBTB) Reg(Bool()) else false.B
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val s2_btb_resp_bits = Reg(new BTBResp)
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val s2_btb_taken = s2_btb_resp_valid && s2_btb_resp_bits.taken
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val s2_tlb_resp = Reg(tlb.io.resp)
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val s2_xcpt = s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst
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val s2_speculative = Reg(init=Bool(false))
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val s2_partial_insn_valid = RegInit(false.B)
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val s2_partial_insn = Reg(UInt(width = coreInstBits))
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val wrong_path = Reg(Bool())
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val s1_base_pc = ~(~s1_pc | (fetchBytes - 1))
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val ntpc = s1_base_pc + fetchBytes.U
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val predicted_npc = Wire(init = ntpc)
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val predicted_taken = Wire(init = Bool(false))
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val s2_replay = Wire(Bool())
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s2_replay := (s2_valid && !fq.io.enq.fire()) || RegNext(s2_replay && !s0_valid, true.B)
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val npc = Mux(s2_replay, s2_pc, predicted_npc)
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s1_pc := io.cpu.npc
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// consider RVC fetches across blocks to be non-speculative if the first
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// part was non-speculative
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val s0_speculative =
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if (usingCompressed) s1_speculative || s2_valid && !s2_speculative || predicted_taken
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else Bool(true)
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s1_speculative := Mux(io.cpu.req.valid, io.cpu.req.bits.speculative, Mux(s2_replay, s2_speculative, s0_speculative))
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val s2_redirect = Wire(init = io.cpu.req.valid)
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s2_valid := false
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when (!s2_replay) {
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s2_valid := !s2_redirect
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s2_pc := s1_pc
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s2_speculative := s1_speculative
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s2_tlb_resp := tlb.io.resp
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}
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io.ptw <> tlb.io.ptw
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tlb.io.req.valid := !s2_replay
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tlb.io.req.bits.vaddr := s1_pc
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tlb.io.req.bits.passthrough := Bool(false)
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tlb.io.req.bits.sfence := io.cpu.sfence
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tlb.io.req.bits.size := log2Ceil(coreInstBytes*fetchWidth)
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icache.io.hartid := io.hartid
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icache.io.req.valid := s0_valid
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icache.io.req.bits.addr := io.cpu.npc
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icache.io.invalidate := io.cpu.flush_icache
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icache.io.s1_paddr := tlb.io.resp.paddr
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icache.io.s2_vaddr := s2_pc
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icache.io.s1_kill := s2_redirect || tlb.io.resp.miss || s2_replay
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icache.io.s2_kill := s2_speculative && !s2_tlb_resp.cacheable || s2_xcpt
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icache.io.s2_prefetch := s2_tlb_resp.prefetchable
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fq.io.enq.valid := RegNext(s1_valid) && s2_valid && (icache.io.resp.valid || !s2_tlb_resp.miss && icache.io.s2_kill)
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fq.io.enq.bits.pc := s2_pc
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io.cpu.npc := alignPC(Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc))
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fq.io.enq.bits.data := icache.io.resp.bits.data
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fq.io.enq.bits.mask := UInt((1 << fetchWidth)-1) << s2_pc.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes))
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fq.io.enq.bits.replay := icache.io.resp.bits.replay || icache.io.s2_kill && !icache.io.resp.valid && !s2_xcpt
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fq.io.enq.bits.btb := s2_btb_resp_bits
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fq.io.enq.bits.btb.taken := s2_btb_taken
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fq.io.enq.bits.xcpt := s2_tlb_resp
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when (icache.io.resp.valid && icache.io.resp.bits.ae) { fq.io.enq.bits.xcpt.ae.inst := true }
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if (usingBTB) {
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val btb = Module(new BTB)
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btb.io.flush := false
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btb.io.req.valid := false
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btb.io.req.bits.addr := s1_pc
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btb.io.btb_update := io.cpu.btb_update
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btb.io.bht_update := io.cpu.bht_update
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btb.io.ras_update.valid := false
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btb.io.bht_advance.valid := false
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when (!s2_replay) {
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btb.io.req.valid := !s2_redirect
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s2_btb_resp_valid := btb.io.resp.valid
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s2_btb_resp_bits := btb.io.resp.bits
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}
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when (btb.io.resp.valid && btb.io.resp.bits.taken) {
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predicted_npc := btb.io.resp.bits.target.sextTo(vaddrBitsExtended)
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predicted_taken := Bool(true)
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}
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val s2_base_pc = ~(~s2_pc | (fetchBytes-1))
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val taken_idx = Wire(UInt())
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val after_idx = Wire(UInt())
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val useRAS = Wire(init=false.B)
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val updateBTB = Wire(init=false.B)
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def scanInsns(idx: Int, prevValid: Bool, prevBits: UInt, prevTaken: Bool): Bool = {
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def insnIsRVC(bits: UInt) = bits(1,0) =/= 3
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val prevRVI = prevValid && !insnIsRVC(prevBits)
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val valid = fq.io.enq.bits.mask(idx) && !prevRVI
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val bits = fq.io.enq.bits.data(coreInstBits*(idx+1)-1, coreInstBits*idx)
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val rvc = insnIsRVC(bits)
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val rviBits = Cat(bits, prevBits)
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val rviBranch = rviBits(6,0) === Instructions.BEQ.value.asUInt()(6,0)
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val rviJump = rviBits(6,0) === Instructions.JAL.value.asUInt()(6,0)
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val rviJALR = rviBits(6,0) === Instructions.JALR.value.asUInt()(6,0)
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val rviReturn = rviJALR && !rviBits(7) && BitPat("b00?01") === rviBits(19,15)
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val rviCall = (rviJALR || rviJump) && rviBits(7)
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val rvcBranch = bits === Instructions.C_BEQZ || bits === Instructions.C_BNEZ
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val rvcJAL = Bool(xLen == 32) && bits === Instructions.C_JAL
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val rvcJump = bits === Instructions.C_J || rvcJAL
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val rvcImm = Mux(bits(14), new RVCDecoder(bits).bImm.asSInt, new RVCDecoder(bits).jImm.asSInt)
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val rvcJR = bits === Instructions.C_MV && bits(6,2) === 0
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val rvcReturn = rvcJR && BitPat("b00?01") === bits(11,7)
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val rvcJALR = bits === Instructions.C_ADD && bits(6,2) === 0
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val rvcCall = rvcJAL || rvcJALR
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val rviImm = Mux(rviBits(3), ImmGen(IMM_UJ, rviBits), ImmGen(IMM_SB, rviBits))
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val taken =
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prevRVI && (rviJump || rviJALR || rviBranch && s2_btb_resp_bits.bht.taken) ||
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valid && (rvcJump || rvcJALR || rvcJR || rvcBranch && s2_btb_resp_bits.bht.taken)
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val predictReturn = btb.io.ras_head.valid && (prevRVI && rviReturn || valid && rvcReturn)
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val predictJump = prevRVI && rviJump || valid && rvcJump
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val predictBranch = s2_btb_resp_bits.bht.taken && (prevRVI && rviBranch || valid && rvcBranch)
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when (s2_valid && s2_btb_resp_valid && s2_btb_resp_bits.bridx === idx && valid && !rvc) {
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// The BTB has predicted that the middle of an RVI instruction is
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// a branch! Flush the BTB and the pipeline.
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btb.io.flush := true
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fq.io.enq.bits.replay := true
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wrong_path := true
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ccover(wrong_path, "BTB_NON_CFI_ON_WRONG_PATH", "BTB predicted a non-branch was taken while on the wrong path")
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}
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when (!prevTaken) {
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taken_idx := idx
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after_idx := idx + 1
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btb.io.ras_update.valid := fq.io.enq.fire() && !wrong_path && (prevRVI && (rviCall || rviReturn) || valid && (rvcCall || rvcReturn))
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btb.io.ras_update.bits.cfiType := Mux(Mux(prevRVI, rviReturn, rvcReturn), CFIType.ret,
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Mux(Mux(prevRVI, rviCall, rvcCall), CFIType.call,
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Mux(Mux(prevRVI, rviBranch, rvcBranch), CFIType.branch,
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CFIType.jump)))
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when (!s2_btb_taken) {
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when (fq.io.enq.fire() && taken && !predictBranch && !predictJump && !predictReturn) {
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wrong_path := true
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}
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when (s2_valid && predictReturn) {
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useRAS := true
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}
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when (s2_valid && (predictBranch || predictJump)) {
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val pc = s2_base_pc | (idx*coreInstBytes)
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val npc =
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if (idx == 0) pc.asSInt + Mux(prevRVI, rviImm -& 2.S, rvcImm)
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else Mux(prevRVI, pc - coreInstBytes, pc).asSInt + Mux(prevRVI, rviImm, rvcImm)
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predicted_npc := npc.asUInt
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}
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}
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when (prevRVI && rviBranch || valid && rvcBranch) {
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btb.io.bht_advance.valid := fq.io.enq.fire() && !wrong_path
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btb.io.bht_advance.bits := s2_btb_resp_bits
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}
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when (!s2_btb_resp_valid && (predictBranch && s2_btb_resp_bits.bht.strongly_taken || predictJump || predictReturn)) {
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updateBTB := true
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}
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}
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if (idx == fetchWidth-1) {
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when (fq.io.enq.fire()) {
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s2_partial_insn_valid := false
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when (valid && !prevTaken && !rvc) {
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s2_partial_insn_valid := true
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s2_partial_insn := bits | 0x3
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}
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}
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prevTaken || taken
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} else {
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scanInsns(idx + 1, valid, bits, prevTaken || taken)
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}
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}
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when (!io.cpu.btb_update.valid) {
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val fetch_bubble_likely = !fq.io.mask(1)
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btb.io.btb_update.valid := fq.io.enq.fire() && !wrong_path && fetch_bubble_likely && updateBTB
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btb.io.btb_update.bits.prediction.entry := UInt(tileParams.btb.get.nEntries)
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btb.io.btb_update.bits.isValid := true
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btb.io.btb_update.bits.cfiType := btb.io.ras_update.bits.cfiType
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btb.io.btb_update.bits.br_pc := s2_base_pc | (taken_idx << log2Ceil(coreInstBytes))
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btb.io.btb_update.bits.pc := s2_base_pc
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}
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btb.io.ras_update.bits.returnAddr := s2_base_pc + (after_idx << log2Ceil(coreInstBytes))
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val taken = scanInsns(0, s2_partial_insn_valid, s2_partial_insn, false.B)
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when (useRAS) {
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predicted_npc := btb.io.ras_head.bits
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}
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when (fq.io.enq.fire() && (s2_btb_taken || taken)) {
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s2_partial_insn_valid := false
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}
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when (!s2_btb_taken) {
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when (taken) {
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fq.io.enq.bits.btb.bridx := taken_idx
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fq.io.enq.bits.btb.taken := true
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fq.io.enq.bits.btb.entry := UInt(tileParams.btb.get.nEntries)
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when (fq.io.enq.fire()) { s2_redirect := true }
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}
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}
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assert(!s2_partial_insn_valid || fq.io.enq.bits.mask(0))
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when (s2_redirect) { s2_partial_insn_valid := false }
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when (io.cpu.req.valid) { wrong_path := false }
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}
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io.cpu.resp <> fq.io.deq
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// performance events
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io.cpu.perf := icache.io.perf
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io.cpu.perf.tlbMiss := io.ptw.req.fire()
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io.errors := icache.io.errors
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def alignPC(pc: UInt) = ~(~pc | (coreInstBytes - 1))
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def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
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cover(cond, s"FRONTEND_$label", "Rocket;;" + desc)
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}
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/** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */
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trait HasICacheFrontend extends CanHavePTW { this: BaseTile =>
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val module: HasICacheFrontendModule
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val frontend = LazyModule(new Frontend(tileParams.icache.get, hartId))
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tlMasterXbar.node := frontend.masterNode
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connectTLSlave(frontend.slaveNode, tileParams.core.fetchBytes)
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nPTWPorts += 1
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}
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trait HasICacheFrontendModule extends CanHavePTWModule {
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val outer: HasICacheFrontend
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ptwPorts += outer.frontend.module.io.ptw
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}
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