riscv/rocket-chip
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Fix BTB error (requires Chisel update)

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This commit is contained in:
Andrew Waterman 2014-05-19 18:56:30 -07:00
parent cbb37ccc3e
commit 8bc1c33540
1 changed files with 4 additions and 6 deletions
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10
rocket/src/main/scala/btb.scala
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@ -146,14 +146,12 @@ class BTB(implicit conf: BTBConfig) extends Module {
val nextRepl = Counter(!updateHit && updateValid, conf.entries)._1 val nextRepl = Counter(!updateHit && updateValid, conf.entries)._1
val waddr = Mux(updateHit, update.bits.prediction.bits.entry, nextRepl) val waddr = Mux(updateHit, update.bits.prediction.bits.entry, nextRepl)
when (doPageRepl) { // invalidate entries if we stomp on pages they depend upon
val clearValid = for (i <- 0 until conf.entries) idxValid := idxValid & ~Vec.tabulate(conf.entries)(i => (pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR).toBits
yield (pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR
idxValid := idxValid & ~Vec(clearValid).toBits idxValid(waddr) := updateValid
}
when (updateTarget) { when (updateTarget) {
assert(io.req === update.bits.target, "BTB request != I$ target") assert(io.req === update.bits.target, "BTB request != I$ target")
idxValid := idxValid.bitSet(waddr, updateValid)
idxs(waddr) := update.bits.pc idxs(waddr) := update.bits.pc
tgts(waddr) := update_target tgts(waddr) := update_target
idxPages(waddr) := idxPageUpdate idxPages(waddr) := idxPageUpdate