From 8bc1c3354024922554f228caa271f6d5f5fd79b9 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@eecs.berkeley.edu>
Date: Mon, 19 May 2014 18:56:30 -0700
Subject: [PATCH] Fix BTB error (requires Chisel update)

---
 rocket/src/main/scala/btb.scala | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/rocket/src/main/scala/btb.scala b/rocket/src/main/scala/btb.scala
index c4de8820..44eb101c 100644
--- a/rocket/src/main/scala/btb.scala
+++ b/rocket/src/main/scala/btb.scala
@@ -146,14 +146,12 @@ class BTB(implicit conf: BTBConfig) extends Module {
     val nextRepl = Counter(!updateHit && updateValid, conf.entries)._1
     val waddr = Mux(updateHit, update.bits.prediction.bits.entry, nextRepl)
 
-    when (doPageRepl) {
-      val clearValid = for (i <- 0 until conf.entries)
-        yield (pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR
-      idxValid := idxValid & ~Vec(clearValid).toBits
-    }
+    // invalidate entries if we stomp on pages they depend upon
+    idxValid := idxValid & ~Vec.tabulate(conf.entries)(i => (pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR).toBits
+
+    idxValid(waddr) := updateValid
     when (updateTarget) {
       assert(io.req === update.bits.target, "BTB request != I$ target")
-      idxValid := idxValid.bitSet(waddr, updateValid)
       idxs(waddr) := update.bits.pc
       tgts(waddr) := update_target
       idxPages(waddr) := idxPageUpdate