fix Hasti and Smi converters
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66b9c5ad05
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@ -403,7 +403,11 @@ class HastiMasterIONastiIOConverter(implicit p: Parameters) extends HastiModule(
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last = (len === UInt(0)))
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last = (len === UInt(0)))
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assert(!r_queue.io.enq.valid || r_queue.io.enq.ready,
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assert(!r_queue.io.enq.valid || r_queue.io.enq.ready,
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"HASTI -> NASTI converter queue overflow")
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"NASTI -> HASTI converter queue overflow")
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val next_count = r_queue.io.count +
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r_queue.io.enq.valid -
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r_queue.io.deq.ready
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io.hasti.haddr := addr
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io.hasti.haddr := addr
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io.hasti.hsize := size
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io.hasti.hsize := size
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@ -418,7 +422,7 @@ class HastiMasterIONastiIOConverter(implicit p: Parameters) extends HastiModule(
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Mux(first, HTRANS_IDLE, HTRANS_BUSY)),
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Mux(first, HTRANS_IDLE, HTRANS_BUSY)),
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s_read -> MuxCase(HTRANS_BUSY, Seq(
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s_read -> MuxCase(HTRANS_BUSY, Seq(
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first -> HTRANS_NONSEQ,
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first -> HTRANS_NONSEQ,
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(r_queue.io.count <= UInt(1)) -> HTRANS_SEQ))))
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(next_count <= UInt(1)) -> HTRANS_SEQ))))
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when (io.nasti.aw.fire()) {
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when (io.nasti.aw.fire()) {
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first := Bool(true)
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first := Bool(true)
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@ -240,16 +240,18 @@ class SmiIONastiWriteIOConverter(val dataWidth: Int, val addrWidth: Int)
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}
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}
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when (state === s_send) {
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when (state === s_send) {
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when (strb === UInt(0)) {
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when (io.smi.req.ready || !strb(0)) {
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state := Mux(last, s_ack, s_data)
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} .elsewhen (io.smi.req.ready || !strb(0)) {
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strb := strb >> jump
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strb := strb >> jump
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data := data >> Cat(jump, UInt(0, log2Up(dataWidth)))
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data := data >> Cat(jump, UInt(0, log2Up(dataWidth)))
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addr := addr + jump
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addr := addr + jump
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when (strb(0)) { state := s_ack }
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}
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}
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}
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}
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when (io.smi.resp.fire()) { state := s_resp }
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when (io.smi.resp.fire()) {
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state := Mux(strb === UInt(0),
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Mux(last, s_resp, s_data), s_send)
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}
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when (io.nasti.b.fire()) { state := s_idle }
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when (io.nasti.b.fire()) { state := s_idle }
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}
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}
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