riscv/rocket-chip
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improvements to implicit RocketConfiguration parameter

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This commit is contained in:
Henry Cook
2012-10-15 16:29:49 -07:00
parent a7a4e65690
commit 8970b635b2
8 changed files with 23 additions and 23 deletions
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12
rocket/src/main/scala/nbdcache.scala
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@ -159,7 +159,7 @@ class MetaArrayReq extends Bundle {
val data = new MetaData()
}
class MSHR(id: Int)(implicit conf: Configuration) extends Component {
class MSHR(id: Int)(implicit conf: RocketConfiguration) extends Component {
val io = new Bundle {
val req_pri_val = Bool(INPUT)
val req_pri_rdy = Bool(OUTPUT)
@ -293,7 +293,7 @@ class MSHR(id: Int)(implicit conf: Configuration) extends Component {
io.replay.bits.way_oh := req.way_oh
}
class MSHRFile()(implicit conf: Configuration) extends Component {
class MSHRFile(implicit conf: RocketConfiguration) extends Component {
val io = new Bundle {
val req = (new FIFOIO) { new MSHRReq }.flip
val secondary_miss = Bool(OUTPUT)
@ -415,7 +415,7 @@ class MSHRFile()(implicit conf: Configuration) extends Component {
}
class WritebackUnit()(implicit conf: Configuration) extends Component {
class WritebackUnit(implicit conf: RocketConfiguration) extends Component {
val io = new Bundle {
val req = (new FIFOIO) { new WritebackReq() }.flip
val probe = (new FIFOIO) { new WritebackReq() }.flip
@ -484,7 +484,7 @@ class WritebackUnit()(implicit conf: Configuration) extends Component {
io.probe_rep_data.bits.data := io.data_resp
}
class ProbeUnit()(implicit conf: Configuration) extends Component {
class ProbeUnit(implicit conf: RocketConfiguration) extends Component {
val io = new Bundle {
val req = (new FIFOIO) { new ProbeRequest }.flip
val rep = (new FIFOIO) { new ProbeReply }
@ -548,7 +548,7 @@ class ProbeUnit()(implicit conf: Configuration) extends Component {
io.wb_req.bits.tag := req.addr >> UFix(IDX_BITS)
}
class FlushUnit(lines: Int)(implicit conf: Configuration) extends Component {
class FlushUnit(lines: Int)(implicit conf: RocketConfiguration) extends Component {
val io = new Bundle {
val req = (new FIFOIO) { Bool() }.flip
val meta_req = (new FIFOIO) { new MetaArrayReq() }
@ -748,7 +748,7 @@ class ioHellaCache extends Bundle {
val xcpt = (new HellaCacheExceptions).asInput
}
class HellaCache()(implicit conf: Configuration) extends Component {
class HellaCache(implicit conf: RocketConfiguration) extends Component {
val io = new Bundle {
val cpu = (new ioHellaCache).flip
val mem = new ioTileLink