From 8970b635b216d6407ea5a11d5672b7ba5f783b83 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 15 Oct 2012 16:29:49 -0700 Subject: [PATCH] improvements to implicit RocketConfiguration parameter --- rocket/src/main/scala/cpu.scala | 8 ++++---- rocket/src/main/scala/dpath.scala | 6 +++--- rocket/src/main/scala/dpath_util.scala | 8 ++++---- rocket/src/main/scala/htif.scala | 4 ++-- rocket/src/main/scala/icache.scala | 2 +- rocket/src/main/scala/nbdcache.scala | 12 ++++++------ rocket/src/main/scala/tile.scala | 2 +- rocket/src/main/scala/top.scala | 4 ++-- 8 files changed, 23 insertions(+), 23 deletions(-) diff --git a/rocket/src/main/scala/cpu.scala b/rocket/src/main/scala/cpu.scala index 8f7f49fc..b9adcd8d 100644 --- a/rocket/src/main/scala/cpu.scala +++ b/rocket/src/main/scala/cpu.scala @@ -5,7 +5,7 @@ import Node._ import Constants._ import hwacha._ -class ioRocket()(implicit conf: Configuration) extends Bundle +class ioRocket(implicit conf: RocketConfiguration) extends Bundle { val host = new ioHTIF() val imem = (new ioImem).flip @@ -13,12 +13,12 @@ class ioRocket()(implicit conf: Configuration) extends Bundle val dmem = new ioHellaCache } -class rocketProc()(implicit conf: Configuration) extends Component +class rocketProc(implicit conf: RocketConfiguration) extends Component { val io = new ioRocket - val ctrl = new rocketCtrl(); - val dpath = new rocketDpath(); + val ctrl = new rocketCtrl + val dpath = new rocketDpath val dtlb = new rocketDTLB(DTLB_ENTRIES); val itlb = new rocketITLB(ITLB_ENTRIES); diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index fc199520..64e45086 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -12,9 +12,9 @@ class ioDpathImem extends Bundle() val resp_data = Bits(INPUT, 32); } -class ioDpathAll()(implicit conf: Configuration) extends Bundle() +class ioDpathAll(implicit conf: RocketConfiguration) extends Bundle { - val host = new ioHTIF() + val host = new ioHTIF val ctrl = new ioCtrlDpath().flip val dmem = new ioHellaCache val dtlb = new ioDTLB_CPU_req_bundle().asOutput() @@ -28,7 +28,7 @@ class ioDpathAll()(implicit conf: Configuration) extends Bundle() val vec_imul_resp = Bits(INPUT, hwacha.Constants.SZ_XLEN) } -class rocketDpath()(implicit conf: Configuration) extends Component +class rocketDpath(implicit conf: RocketConfiguration) extends Component { val io = new ioDpathAll(); diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index 66e6dec9..e0e2b84a 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -57,9 +57,9 @@ class rocketDpathBTB(entries: Int) extends Component io.target := mux.io.out.toUFix } -class ioDpathPCR()(implicit conf: Configuration) extends Bundle() +class ioDpathPCR(implicit conf: RocketConfiguration) extends Bundle { - val host = new ioHTIF() + val host = new ioHTIF val r = new ioReadPort(); val w = new ioWritePort(); @@ -86,9 +86,9 @@ class ioDpathPCR()(implicit conf: Configuration) extends Bundle() val vec_nfregs = UFix(INPUT, 6) } -class rocketDpathPCR()(implicit conf: Configuration) extends Component +class rocketDpathPCR(implicit conf: RocketConfiguration) extends Component { - val io = new ioDpathPCR(); + val io = new ioDpathPCR val reg_epc = Reg() { UFix() }; val reg_badvaddr = Reg() { UFix() }; diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala index 761bb59d..5f2a3e35 100644 --- a/rocket/src/main/scala/htif.scala +++ b/rocket/src/main/scala/htif.scala @@ -23,7 +23,7 @@ class PCRReq extends Bundle val data = Bits(width = 64) } -class ioHTIF()(implicit conf: Configuration) extends Bundle +class ioHTIF(implicit conf: RocketConfiguration) extends Bundle { val reset = Bool(INPUT) val debug = new ioDebug @@ -33,7 +33,7 @@ class ioHTIF()(implicit conf: Configuration) extends Bundle val ipi_rep = (new FIFOIO) { Bool() }.flip } -class rocketHTIF(w: Int)(implicit conf: Configuration) extends Component +class rocketHTIF(w: Int)(implicit conf: RocketConfiguration) extends Component { val io = new Bundle { val host = new ioHost(w) diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index c0fa675e..6b3894ca 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -28,7 +28,7 @@ class ioRocketICache extends Bundle() // 32 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines // parameters : // lines = # cache lines -class rocketICache(sets: Int, assoc: Int)(implicit conf: Configuration) extends Component +class rocketICache(sets: Int, assoc: Int)(implicit conf: RocketConfiguration) extends Component { val io = new ioRocketICache(); diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index a2f0839a..6c68c302 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -159,7 +159,7 @@ class MetaArrayReq extends Bundle { val data = new MetaData() } -class MSHR(id: Int)(implicit conf: Configuration) extends Component { +class MSHR(id: Int)(implicit conf: RocketConfiguration) extends Component { val io = new Bundle { val req_pri_val = Bool(INPUT) val req_pri_rdy = Bool(OUTPUT) @@ -293,7 +293,7 @@ class MSHR(id: Int)(implicit conf: Configuration) extends Component { io.replay.bits.way_oh := req.way_oh } -class MSHRFile()(implicit conf: Configuration) extends Component { +class MSHRFile(implicit conf: RocketConfiguration) extends Component { val io = new Bundle { val req = (new FIFOIO) { new MSHRReq }.flip val secondary_miss = Bool(OUTPUT) @@ -415,7 +415,7 @@ class MSHRFile()(implicit conf: Configuration) extends Component { } -class WritebackUnit()(implicit conf: Configuration) extends Component { +class WritebackUnit(implicit conf: RocketConfiguration) extends Component { val io = new Bundle { val req = (new FIFOIO) { new WritebackReq() }.flip val probe = (new FIFOIO) { new WritebackReq() }.flip @@ -484,7 +484,7 @@ class WritebackUnit()(implicit conf: Configuration) extends Component { io.probe_rep_data.bits.data := io.data_resp } -class ProbeUnit()(implicit conf: Configuration) extends Component { +class ProbeUnit(implicit conf: RocketConfiguration) extends Component { val io = new Bundle { val req = (new FIFOIO) { new ProbeRequest }.flip val rep = (new FIFOIO) { new ProbeReply } @@ -548,7 +548,7 @@ class ProbeUnit()(implicit conf: Configuration) extends Component { io.wb_req.bits.tag := req.addr >> UFix(IDX_BITS) } -class FlushUnit(lines: Int)(implicit conf: Configuration) extends Component { +class FlushUnit(lines: Int)(implicit conf: RocketConfiguration) extends Component { val io = new Bundle { val req = (new FIFOIO) { Bool() }.flip val meta_req = (new FIFOIO) { new MetaArrayReq() } @@ -748,7 +748,7 @@ class ioHellaCache extends Bundle { val xcpt = (new HellaCacheExceptions).asInput } -class HellaCache()(implicit conf: Configuration) extends Component { +class HellaCache(implicit conf: RocketConfiguration) extends Component { val io = new Bundle { val cpu = (new ioHellaCache).flip val mem = new ioTileLink diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index 69aef22d..0a37db2a 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -5,7 +5,7 @@ import Node._ import Constants._ import uncore._ -class Tile(resetSignal: Bool = null)(implicit conf: Configuration) extends Component(resetSignal) +class Tile(resetSignal: Bool = null)(implicit conf: RocketConfiguration) extends Component(resetSignal) { val io = new Bundle { val tilelink = new ioTileLink diff --git a/rocket/src/main/scala/top.scala b/rocket/src/main/scala/top.scala index 7b29021c..df6f084d 100644 --- a/rocket/src/main/scala/top.scala +++ b/rocket/src/main/scala/top.scala @@ -13,7 +13,7 @@ object DummyTopLevelConstants extends rocket.constants.CoherenceConfigConstants } import DummyTopLevelConstants._ -case class Configuration(ntiles: Int, co: CoherencePolicyWithUncached) +case class RocketConfiguration(ntiles: Int, co: CoherencePolicyWithUncached) class Top extends Component { @@ -24,7 +24,7 @@ class Top extends Component if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence else new MICoherence } - implicit val conf = Configuration(NTILES, co) + implicit val conf = RocketConfiguration(NTILES, co) val io = new Bundle { val debug = new ioDebug