riscv/rocket-chip
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improvements to implicit RocketConfiguration parameter

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This commit is contained in:
Henry Cook
2012-10-15 16:29:49 -07:00
parent a7a4e65690
commit 8970b635b2
8 changed files with 23 additions and 23 deletions
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rocket/src/main/scala/icache.scala
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@ -28,7 +28,7 @@ class ioRocketICache extends Bundle()
// 32 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines
// parameters :
// lines = # cache lines
class rocketICache(sets: Int, assoc: Int)(implicit conf: Configuration) extends Component
class rocketICache(sets: Int, assoc: Int)(implicit conf: RocketConfiguration) extends Component
{
val io = new ioRocketICache();