riscv/rocket-chip
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replace remaining uses of Vec.fill

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This commit is contained in:
Howard Mao 2015-09-24 17:51:38 -07:00
parent e3d2207c72
commit 88b15dba60
2 changed files with 3 additions and 3 deletions
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4
junctions/src/main/scala/nasti.scala
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@ -481,8 +481,8 @@ class NASTICrossbar(nMasters: Int, nSlaves: Int, addrmap: Seq[(BigInt, BigInt)])
val slaves = Vec(new NASTIIO, nSlaves) val slaves = Vec(new NASTIIO, nSlaves)
} }
val routers = Vec.fill(nMasters) { Module(new NASTIRouter(addrmap)).io } val routers = Vec(nMasters, Module(new NASTIRouter(addrmap)).io)
val arbiters = Vec.fill(nSlaves) { Module(new NASTIArbiter(nMasters)).io } val arbiters = Vec(nSlaves, Module(new NASTIArbiter(nMasters)).io)
for (i <- 0 until nMasters) { for (i <- 0 until nMasters) {
routers(i).master <> io.masters(i) routers(i).master <> io.masters(i)

2
junctions/src/main/scala/smi.scala
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@ -116,7 +116,7 @@ class SMIIONASTIReadIOConverter(val dataWidth: Int, val addrWidth: Int)
val recvInd = Reg(init = UInt(0, wordCountBits)) val recvInd = Reg(init = UInt(0, wordCountBits))
val sendDone = Reg(init = Bool(false)) val sendDone = Reg(init = Bool(false))
val buffer = Reg(init = Vec.fill(maxWordsPerBeat) { Bits(0, dataWidth) }) val buffer = Reg(init = Vec(maxWordsPerBeat, Bits(0, dataWidth)))
io.ar.ready := (state === s_idle) io.ar.ready := (state === s_idle)