diff --git a/junctions/src/main/scala/nasti.scala b/junctions/src/main/scala/nasti.scala
index f3e9f65f..abda7321 100644
--- a/junctions/src/main/scala/nasti.scala
+++ b/junctions/src/main/scala/nasti.scala
@@ -481,8 +481,8 @@ class NASTICrossbar(nMasters: Int, nSlaves: Int, addrmap: Seq[(BigInt, BigInt)])
     val slaves = Vec(new NASTIIO, nSlaves)
   }
 
-  val routers = Vec.fill(nMasters) { Module(new NASTIRouter(addrmap)).io }
-  val arbiters = Vec.fill(nSlaves) { Module(new NASTIArbiter(nMasters)).io }
+  val routers = Vec(nMasters, Module(new NASTIRouter(addrmap)).io)
+  val arbiters = Vec(nSlaves, Module(new NASTIArbiter(nMasters)).io)
 
   for (i <- 0 until nMasters) {
     routers(i).master <> io.masters(i)
diff --git a/junctions/src/main/scala/smi.scala b/junctions/src/main/scala/smi.scala
index ec2e554e..b7dc329d 100644
--- a/junctions/src/main/scala/smi.scala
+++ b/junctions/src/main/scala/smi.scala
@@ -116,7 +116,7 @@ class SMIIONASTIReadIOConverter(val dataWidth: Int, val addrWidth: Int)
   val recvInd = Reg(init = UInt(0, wordCountBits))
   val sendDone = Reg(init = Bool(false))
 
-  val buffer = Reg(init = Vec.fill(maxWordsPerBeat) { Bits(0, dataWidth) })
+  val buffer = Reg(init = Vec(maxWordsPerBeat, Bits(0, dataWidth)))
 
   io.ar.ready := (state === s_idle)