riscv/rocket-chip
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make sure TraceGen addresses are correct

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This commit is contained in:
Howard Mao 2016-05-20 16:12:11 -07:00
parent 3e759d2575
commit 87be2bcd60
1 changed files with 3 additions and 1 deletions
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4
groundtest/src/main/scala/tracegen.scala
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@ -185,7 +185,9 @@ class TraceGenerator(id: Int)
// Address bag, shared by all cores, taken from module parameters. // Address bag, shared by all cores, taken from module parameters.
// In addition, there is a per-core random selection of extra addresses. // In addition, there is a per-core random selection of extra addresses.
val bagOfAddrs = addressBag.map(x => UInt(x, numBitsInWord)) val addrHashMap = p(GlobalAddrHashMap)
val memStart = addrHashMap("mem").start
val bagOfAddrs = addressBag.map(x => UInt(memStart + x, numBitsInWord))
val extraAddrs = (0 to numExtraAddrs-1). val extraAddrs = (0 to numExtraAddrs-1).
map(i => Reg(UInt(width = 16))) map(i => Reg(UInt(width = 16)))