From 87be2bcd6036ab1744b64ba825af571e4d35ad7f Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Fri, 20 May 2016 16:12:11 -0700 Subject: [PATCH] make sure TraceGen addresses are correct --- groundtest/src/main/scala/tracegen.scala | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/groundtest/src/main/scala/tracegen.scala b/groundtest/src/main/scala/tracegen.scala index fd3db353..9f766bbe 100644 --- a/groundtest/src/main/scala/tracegen.scala +++ b/groundtest/src/main/scala/tracegen.scala @@ -185,7 +185,9 @@ class TraceGenerator(id: Int) // Address bag, shared by all cores, taken from module parameters. // In addition, there is a per-core random selection of extra addresses. - val bagOfAddrs = addressBag.map(x => UInt(x, numBitsInWord)) + val addrHashMap = p(GlobalAddrHashMap) + val memStart = addrHashMap("mem").start + val bagOfAddrs = addressBag.map(x => UInt(memStart + x, numBitsInWord)) val extraAddrs = (0 to numExtraAddrs-1). map(i => Reg(UInt(width = 16)))