From 8766438bb98684632eb3950997256bf7471ba101 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 23 Jan 2012 09:51:35 -0800 Subject: [PATCH] Updated chisel removes ^^ from language. Removed from rocket source, updated jar. --- rocket/src/main/scala/cpu.scala | 6 +++--- rocket/src/main/scala/dcache.scala | 4 ++-- rocket/src/main/scala/dpath.scala | 16 ++++++++-------- rocket/src/main/scala/nbdcache.scala | 7 ++++--- rocket/src/main/scala/queues.scala | 26 +++++++++++++------------- rocket/src/main/scala/top.scala | 8 ++++---- rocket/src/main/scala/util.scala | 4 ++-- 7 files changed, 36 insertions(+), 35 deletions(-) diff --git a/rocket/src/main/scala/cpu.scala b/rocket/src/main/scala/cpu.scala index b93392ff..e8a99954 100644 --- a/rocket/src/main/scala/cpu.scala +++ b/rocket/src/main/scala/cpu.scala @@ -45,8 +45,8 @@ class rocketProc extends Component val arb = new rocketDmemArbiter(); ctrl.io.dpath <> dpath.io.ctrl; - dpath.io.host ^^ io.host; - dpath.io.debug ^^ io.debug; + dpath.io.host <> io.host; + dpath.io.debug <> io.debug; // FIXME: try to make this more compact @@ -86,7 +86,7 @@ class rocketProc extends Component ptw.io.itlb <> itlb.io.ptw; ptw.io.ptbr := dpath.io.ptbr; arb.io.ptw <> ptw.io.dmem; - arb.io.mem ^^ io.dmem + arb.io.mem <> io.dmem // connect arbiter to ctrl+dpath+DTLB arb.io.cpu.req_val := ctrl.io.dmem.req_val; diff --git a/rocket/src/main/scala/dcache.scala b/rocket/src/main/scala/dcache.scala index 73fd4f61..8f0ac992 100644 --- a/rocket/src/main/scala/dcache.scala +++ b/rocket/src/main/scala/dcache.scala @@ -162,9 +162,9 @@ class rocketDCacheDM_flush(lines: Int) extends Component { dcache.io.cpu.req_ppn := Mux(flushing, UFix(0,PPN_BITS), io.cpu.req_ppn); dcache.io.cpu.req_tag := Mux(flushing, r_cpu_req_tag, io.cpu.req_tag); dcache.io.cpu.req_type := io.cpu.req_type; - dcache.io.cpu.req_data ^^ io.cpu.req_data; + dcache.io.cpu.req_data <> io.cpu.req_data; dcache.io.cpu.req_kill := io.cpu.req_kill && !flush_waiting; - dcache.io.mem ^^ io.mem; + dcache.io.mem <> io.mem; io.cpu.xcpt_ma_ld := dcache.io.cpu.xcpt_ma_ld; io.cpu.xcpt_ma_st := dcache.io.cpu.xcpt_ma_st; diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index b0bab419..06b38a0d 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -163,9 +163,9 @@ class rocketDpath extends Component if_next_pc.toUFix); btb.io.current_pc4 := if_pc_plus4; - btb.io.hit ^^ io.ctrl.btb_hit; - btb.io.wen ^^ io.ctrl.wen_btb; - btb.io.clr ^^ io.ctrl.clr_btb; + btb.io.hit <> io.ctrl.btb_hit; + btb.io.wen <> io.ctrl.wen_btb; + btb.io.clr <> io.ctrl.clr_btb; btb.io.correct_pc4 := ex_reg_pc_plus4; io.ctrl.btb_match := id_reg_pc === jr_br_target; @@ -187,11 +187,11 @@ class rocketDpath extends Component val id_raddr2 = id_reg_inst(21,17).toUFix; // regfile read - rfile.io.r0.en ^^ io.ctrl.ren2; + rfile.io.r0.en <> io.ctrl.ren2; rfile.io.r0.addr := id_raddr2; val id_rdata2 = rfile.io.r0.data; - rfile.io.r1.en ^^ io.ctrl.ren1; + rfile.io.r1.en <> io.ctrl.ren1; rfile.io.r1.addr := id_raddr1; val id_rdata1 = rfile.io.r1.data; @@ -324,9 +324,9 @@ class rocketDpath extends Component Mux(ex_reg_ctrl_eret, PCR_EPC, ex_reg_raddr2); - pcr.io.host.from_wen ^^ io.host.from_wen; - pcr.io.host.from ^^ io.host.from; - pcr.io.host.to ^^ io.host.to; + pcr.io.host.from_wen <> io.host.from_wen; + pcr.io.host.from <> io.host.from; + pcr.io.host.to <> io.host.to; io.ctrl.irq_timer := pcr.io.irq_timer; io.ctrl.irq_ipi := pcr.io.irq_ipi; diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index e75ea972..29334429 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -341,9 +341,9 @@ class MSHRFile extends Component { alloc_arb.io.out.ready := io.req_val && !idx_match - meta_req_arb.io.out ^^ io.meta_req - mem_req_arb.io.out ^^ io.mem_req - replay_arb.io.out ^^ io.replay + meta_req_arb.io.out <> io.meta_req + mem_req_arb.io.out <> io.mem_req + replay_arb.io.out <> io.replay io.req_rdy := Mux(idx_match, tag_match && sec_rdy, pri_rdy) io.mem_resp_idx := mem_resp_idx_mux.io.out @@ -810,6 +810,7 @@ class HellaCacheDM(lines: Int) extends Component { p_store_type <== r_cpu_req_type p_store_cmd <== r_cpu_req_cmd p_store_data <== storegen.io.dout + p_store_way_id <== UFix(0) } // miss handling diff --git a/rocket/src/main/scala/queues.scala b/rocket/src/main/scala/queues.scala index 3f6892f9..90732f2e 100644 --- a/rocket/src/main/scala/queues.scala +++ b/rocket/src/main/scala/queues.scala @@ -93,13 +93,13 @@ class queueSimplePF[T <: Data](entries: Int)(data: => T) extends Component { override val io = new ioQueueSimplePF()(data); val ctrl = new queueCtrl(entries); - ctrl.io.q_reset ^^ io.q_reset; - ctrl.io.deq_val ^^ io.deq.valid; - ctrl.io.enq_rdy ^^ io.enq.ready; - ctrl.io.enq_val ^^ io.enq.valid; - ctrl.io.deq_rdy ^^ io.deq.ready; + ctrl.io.q_reset <> io.q_reset; + ctrl.io.deq_val <> io.deq.valid; + ctrl.io.enq_rdy <> io.enq.ready; + ctrl.io.enq_val <> io.enq.valid; + ctrl.io.deq_rdy <> io.deq.ready; val ram = Mem(entries, ctrl.io.wen, ctrl.io.waddr, io.enq.bits); - ram.read(ctrl.io.raddr) ^^ io.deq.bits; + ram.read(ctrl.io.raddr) <> io.deq.bits; } // TODO: SHOULD USE INHERITANCE BUT BREAKS INTROSPECTION CODE @@ -191,7 +191,7 @@ class queueDpathFlow[T <: Data](entries: Int)(data: => T) extends Component override val io = new ioQueueDpathFlow(addr_sz)(data); val ram = Mem(entries, io.wen, io.waddr, io.enq_bits); val rout = ram(io.raddr); - Mux(io.flowthru, io.enq_bits, rout) ^^ io.deq_bits; + Mux(io.flowthru, io.enq_bits, rout) <> io.deq_bits; } class ioQueueFlowPF[T <: Data](data: => T) extends Bundle() @@ -210,17 +210,17 @@ class queueFlowPF[T <: Data](entries: Int)(data: => T) extends Component val ctrl = new queueCtrlFlow(entries); val dpath = new queueDpathFlow(entries)(data); - ctrl.io.deq_rdy ^^ io.deq_rdy; + ctrl.io.deq_rdy <> io.deq_rdy; ctrl.io.wen <> dpath.io.wen; ctrl.io.raddr <> dpath.io.raddr; ctrl.io.waddr <> dpath.io.waddr; ctrl.io.flowthru <> dpath.io.flowthru; - ctrl.io.enq_val ^^ io.enq_val; - dpath.io.enq_bits ^^ io.enq_bits; + ctrl.io.enq_val <> io.enq_val; + dpath.io.enq_bits <> io.enq_bits; - ctrl.io.deq_val ^^ io.deq_val; - ctrl.io.enq_rdy ^^ io.enq_rdy; - dpath.io.deq_bits ^^ io.deq_bits; + ctrl.io.deq_val <> io.deq_val; + ctrl.io.enq_rdy <> io.enq_rdy; + dpath.io.deq_bits <> io.deq_bits; } } diff --git a/rocket/src/main/scala/top.scala b/rocket/src/main/scala/top.scala index be9bb311..daa049be 100644 --- a/rocket/src/main/scala/top.scala +++ b/rocket/src/main/scala/top.scala @@ -20,13 +20,13 @@ class Top() extends Component { val dcache = new HellaCacheDM(128); val arbiter = new rocketMemArbiter(); - arbiter.io.mem ^^ io.mem; + arbiter.io.mem <> io.mem; arbiter.io.dcache <> dcache.io.mem; arbiter.io.icache <> icache_pf.io.mem; - cpu.io.host ^^ io.host; - cpu.io.debug ^^ io.debug; - cpu.io.console ^^ io.console; + cpu.io.host <> io.host; + cpu.io.debug <> io.debug; + cpu.io.console <> io.console; icache.io.mem <> icache_pf.io.icache; cpu.io.imem <> icache.io.cpu; diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala index f9ddab80..837af57a 100644 --- a/rocket/src/main/scala/util.scala +++ b/rocket/src/main/scala/util.scala @@ -102,8 +102,8 @@ class Arbiter[T <: Data](n: Int)(data: => T) extends Component { for (i <- 1 to n-1) vout = vout || io.in(i).valid - vout ^^ io.out.valid - dout ^^ io.out.bits + vout <> io.out.valid + dout <> io.out.bits } class ioPriorityDecoder(in_width: Int, out_width: Int) extends Bundle