riscv/rocket-chip
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clean up ioDecoupled/ioPipe interface

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This commit is contained in:
Yunsup Lee
2012-03-01 20:48:46 -08:00
parent 6d03d75835
commit 8678b3d70c
13 changed files with 73 additions and 73 deletions
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16
rocket/src/main/scala/util.scala
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@ -168,20 +168,20 @@ class Mux1H [T <: Data](n: Int)(gen: => T) extends Component
class ioDecoupled[+T <: Data]()(data: => T) extends Bundle
{
val valid = Bool(INPUT)
val ready = Bool(OUTPUT)
val bits = data.asInput
val ready = Bool(INPUT)
val valid = Bool(OUTPUT)
val bits = data.asOutput
}
class ioValid[T <: Data]()(data: => T) extends Bundle
class ioPipe[T <: Data]()(data: => T) extends Bundle
{
val valid = Bool(INPUT)
val bits = data.asInput
}
class ioArbiter[T <: Data](n: Int)(data: => T) extends Bundle {
val in = Vec(n) { (new ioDecoupled()) { data } }
val out = (new ioDecoupled()) { data }.flip()
val in = Vec(n) { (new ioDecoupled()) { data } }.flip
val out = (new ioDecoupled()) { data }
}
class Arbiter[T <: Data](n: Int)(data: => T) extends Component {
@ -205,9 +205,9 @@ class Arbiter[T <: Data](n: Int)(data: => T) extends Component {
}
class ioLockingArbiter[T <: Data](n: Int)(data: => T) extends Bundle {
val in = Vec(n) { (new ioDecoupled()) { data } }
val in = Vec(n) { (new ioDecoupled()) { data } }.flip
val lock = Vec(n) { Bool() }.asInput
val out = (new ioDecoupled()) { data }.flip()
val out = (new ioDecoupled()) { data }
}
class LockingArbiter[T <: Data](n: Int)(data: => T) extends Component {