diff --git a/rocket/src/main/scala/coherence.scala b/rocket/src/main/scala/coherence.scala
index 2c5c6edf..97d098bd 100644
--- a/rocket/src/main/scala/coherence.scala
+++ b/rocket/src/main/scala/coherence.scala
@@ -21,9 +21,9 @@ class MemResp () extends MemData
 
 class ioMem() extends Bundle
 {
-  val req_cmd  = (new ioDecoupled) { new MemReqCmd() }.flip
-  val req_data = (new ioDecoupled) { new MemData() }.flip
-  val resp     = (new ioValid) { new MemResp() }
+  val req_cmd  = (new ioDecoupled) { new MemReqCmd() }
+  val req_data = (new ioDecoupled) { new MemData() }
+  val resp     = (new ioPipe) { new MemResp() }
 }
 
 class HubMemReq extends Bundle {
@@ -80,14 +80,14 @@ class TransactionFinish extends Bundle {
 }
 
 class ioTileLink extends Bundle { 
-  val xact_init      = (new ioDecoupled) { new TransactionInit() }.flip
-  val xact_init_data = (new ioDecoupled) { new TransactionInitData() }.flip
-  val xact_abort     = (new ioDecoupled) { new TransactionAbort() }
-  val probe_req      = (new ioDecoupled) { new ProbeRequest() }
-  val probe_rep      = (new ioDecoupled) { new ProbeReply() }.flip
-  val probe_rep_data = (new ioDecoupled) { new ProbeReplyData() }.flip
-  val xact_rep       = (new ioValid)     { new TransactionReply() }
-  val xact_finish    = (new ioDecoupled) { new TransactionFinish() }.flip
+  val xact_init      = (new ioDecoupled) { new TransactionInit() }
+  val xact_init_data = (new ioDecoupled) { new TransactionInitData() }
+  val xact_abort     = (new ioDecoupled) { new TransactionAbort() }.flip
+  val probe_req      = (new ioDecoupled) { new ProbeRequest() }.flip
+  val probe_rep      = (new ioDecoupled) { new ProbeReply() }
+  val probe_rep_data = (new ioDecoupled) { new ProbeReplyData() }
+  val xact_rep       = (new ioPipe)     { new TransactionReply() }
+  val xact_finish    = (new ioDecoupled) { new TransactionFinish() }
 }
 
 object cpuCmdToRW {
@@ -181,20 +181,20 @@ trait FourStateCoherence extends CoherencePolicy {
 
 class XactTracker(id: Int) extends Component with CoherencePolicy {
   val io = new Bundle {
-    val alloc_req       = (new ioDecoupled) { new TrackerAllocReq() }
+    val alloc_req       = (new ioDecoupled) { new TrackerAllocReq() }.flip
     val probe_data      = (new TrackerProbeData).asInput
     val can_alloc       = Bool(INPUT)
     val xact_finish     = Bool(INPUT)
     val p_rep_cnt_dec   = Bits(NTILES, INPUT)
     val p_req_cnt_inc   = Bits(NTILES, INPUT)
-    val p_rep_data      = (new ioDecoupled) { new ProbeReplyData() }
-    val x_init_data     = (new ioDecoupled) { new TransactionInitData() }
+    val p_rep_data      = (new ioDecoupled) { new ProbeReplyData() }.flip
+    val x_init_data     = (new ioDecoupled) { new TransactionInitData() }.flip
     val sent_x_rep_ack  = Bool(INPUT)
 
-    val mem_req_cmd     = (new ioDecoupled) { new MemReqCmd() }.flip
-    val mem_req_data    = (new ioDecoupled) { new MemData() }.flip
+    val mem_req_cmd     = (new ioDecoupled) { new MemReqCmd() }
+    val mem_req_data    = (new ioDecoupled) { new MemData() }
     val mem_req_lock    = Bool(OUTPUT)
-    val probe_req       = (new ioDecoupled) { new ProbeRequest() }.flip
+    val probe_req       = (new ioDecoupled) { new ProbeRequest() }
     val busy            = Bool(OUTPUT)
     val addr            = Bits(PADDR_BITS, OUTPUT)
     val init_tile_id    = Bits(TILE_ID_BITS, OUTPUT)
diff --git a/rocket/src/main/scala/cpu.scala b/rocket/src/main/scala/cpu.scala
index 7cb9090e..b6d1a9e2 100644
--- a/rocket/src/main/scala/cpu.scala
+++ b/rocket/src/main/scala/cpu.scala
@@ -14,9 +14,9 @@ class ioRocket extends Bundle()
 {
   val debug   = new ioDebug();
   val host    = new ioHTIF();
-  val imem    = new ioImem().flip();
-  val vimem   = new ioImem().flip();
-  val dmem    = new ioDmem().flip();
+  val imem    = new ioImem().flip
+  val vimem   = new ioImem().flip
+  val dmem    = new ioDmem().flip
 }
 
 class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala
index 119d5b1e..ac544a68 100644
--- a/rocket/src/main/scala/ctrl.scala
+++ b/rocket/src/main/scala/ctrl.scala
@@ -77,8 +77,8 @@ class ioCtrlDpath extends Bundle()
 class ioCtrlAll extends Bundle()
 {
   val dpath   = new ioCtrlDpath();
-  val imem    = new ioImem(List("req_val", "resp_val")).flip();
-  val dmem    = new ioDmem(List("req_val", "req_kill", "req_rdy", "req_cmd", "req_type", "resp_miss", "resp_nack", "xcpt_ma_ld", "xcpt_ma_st")).flip();
+  val imem    = new ioImem(List("req_val", "resp_val")).flip
+  val dmem    = new ioDmem(List("req_val", "req_kill", "req_rdy", "req_cmd", "req_type", "resp_miss", "resp_nack", "xcpt_ma_ld", "xcpt_ma_st")).flip
   val dtlb_val = Bool(OUTPUT);
   val dtlb_kill = Bool(OUTPUT);
   val dtlb_rdy = Bool(INPUT);
diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala
index 1a3d5cee..817e001b 100644
--- a/rocket/src/main/scala/dpath.scala
+++ b/rocket/src/main/scala/dpath.scala
@@ -16,15 +16,15 @@ class ioDpathImem extends Bundle()
 class ioDpathAll extends Bundle()
 {
   val host  = new ioHTIF();
-  val ctrl  = new ioCtrlDpath().flip();
+  val ctrl  = new ioCtrlDpath().flip
   val debug = new ioDebug();
-  val dmem  = new ioDmem(List("req_idx", "req_tag", "req_data", "resp_val", "resp_miss", "resp_replay", "resp_type", "resp_tag", "resp_data", "resp_data_subword")).flip();
+  val dmem  = new ioDmem(List("req_idx", "req_tag", "req_data", "resp_val", "resp_miss", "resp_replay", "resp_type", "resp_tag", "resp_data", "resp_data_subword")).flip
   val dtlb = new ioDTLB_CPU_req_bundle().asOutput()
   val imem  = new ioDpathImem();
   val ptbr_wen = Bool(OUTPUT);
   val ptbr = UFix(PADDR_BITS, OUTPUT);
   val fpu = new ioDpathFPU();
-  val vec_ctrl = new ioCtrlDpathVec().flip()
+  val vec_ctrl = new ioCtrlDpathVec().flip
   val vec_iface = new ioDpathVecInterface()
   val vec_imul_req = new io_imul_req
   val vec_imul_resp = Bits(hwacha.Constants.SZ_XLEN, INPUT)
diff --git a/rocket/src/main/scala/dpath_vec.scala b/rocket/src/main/scala/dpath_vec.scala
index c68db9de..ddb629ff 100644
--- a/rocket/src/main/scala/dpath_vec.scala
+++ b/rocket/src/main/scala/dpath_vec.scala
@@ -17,7 +17,7 @@ class ioDpathVecInterface extends Bundle
 
 class ioDpathVec extends Bundle
 {
-  val ctrl = new ioCtrlDpathVec().flip()
+  val ctrl = new ioCtrlDpathVec().flip
   val iface = new ioDpathVecInterface()
   val valid = Bool(INPUT)
   val inst = Bits(32, INPUT)
diff --git a/rocket/src/main/scala/dtlb.scala b/rocket/src/main/scala/dtlb.scala
index eb7a91cf..50844713 100644
--- a/rocket/src/main/scala/dtlb.scala
+++ b/rocket/src/main/scala/dtlb.scala
@@ -17,7 +17,7 @@ class ioDTLB_CPU_req_bundle extends Bundle
   val asid = Bits(width=ASID_BITS)
   val vpn  = Bits(width=VPN_BITS+1)
 }
-class ioDTLB_CPU_req extends io_ready_valid()( { new ioDTLB_CPU_req_bundle() } )
+class ioDTLB_CPU_req extends hwacha.ioDecoupled()( { new ioDTLB_CPU_req_bundle() } )
 
 class ioDTLB_CPU_resp extends Bundle
 {
@@ -34,7 +34,7 @@ class ioDTLB extends Bundle
   val status = Bits(17,INPUT)
   // invalidate all TLB entries
   val invalidate = Bool(INPUT)
-  val cpu_req = new ioDTLB_CPU_req().flip()
+  val cpu_req = new ioDTLB_CPU_req().flip
   val cpu_resp = new ioDTLB_CPU_resp()
   val ptw = new ioTLB_PTW()
 }
diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala
index e45355fa..bf81d49e 100644
--- a/rocket/src/main/scala/fpu.scala
+++ b/rocket/src/main/scala/fpu.scala
@@ -445,8 +445,8 @@ class rocketFPUDFMAPipe(latency: Int) extends Component
 class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
 {
   val io = new Bundle {
-    val ctrl = new ioCtrlFPU().flip()
-    val dpath = new ioDpathFPU().flip()
+    val ctrl = new ioCtrlFPU().flip
+    val dpath = new ioDpathFPU().flip
     val sfma = new ioFMA(33)
     val dfma = new ioFMA(65)
   }
diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala
index 551f3d25..0357d359 100644
--- a/rocket/src/main/scala/htif.scala
+++ b/rocket/src/main/scala/htif.scala
@@ -6,8 +6,8 @@ import Constants._;
 
 class ioHost(w: Int, view: List[String] = null) extends Bundle(view)
 {
-  val in = new ioDecoupled()(Bits(width = w))
-  val out = new ioDecoupled()(Bits(width = w)).flip()
+  val in = new ioDecoupled()(Bits(width = w)).flip
+  val out = new ioDecoupled()(Bits(width = w))
 }
 
 class ioHTIF extends Bundle
@@ -25,7 +25,7 @@ class rocketHTIF(w: Int, ncores: Int) extends Component
 {
   val io = new Bundle {
     val host = new ioHost(w)
-    val cpu = Vec(ncores) { new ioHTIF().flip() }
+    val cpu = Vec(ncores) { new ioHTIF().flip }
     val mem = new ioTileLink
   }
 
diff --git a/rocket/src/main/scala/multiplier.scala b/rocket/src/main/scala/multiplier.scala
index 0138afd0..a29ab658 100644
--- a/rocket/src/main/scala/multiplier.scala
+++ b/rocket/src/main/scala/multiplier.scala
@@ -7,7 +7,7 @@ import hwacha._
 import hwacha.Constants._
 
 class ioMultiplier extends Bundle {
-  val req = new io_imul_req().flip()
+  val req = new io_imul_req().flip
   val req_tag = Bits(5, INPUT)
   val req_kill = Bool(INPUT)
   val resp_val = Bool(OUTPUT)
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index 08067420..e928360c 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -178,9 +178,9 @@ class MSHR(id: Int) extends Component with ThreeStateIncoherence {
     val way_oh         = Bits(NWAYS, OUTPUT)
 
     val mem_resp_val = Bool(INPUT)
-    val mem_req  = (new ioDecoupled) { new TransactionInit }.flip
-    val meta_req = (new ioDecoupled) { new MetaArrayArrayReq() }.flip
-    val replay   = (new ioDecoupled) { new Replay()   }.flip
+    val mem_req  = (new ioDecoupled) { new TransactionInit }
+    val meta_req = (new ioDecoupled) { new MetaArrayArrayReq() }
+    val replay   = (new ioDecoupled) { new Replay()   }
   }
 
   val valid = Reg(resetVal = Bool(false))
@@ -253,7 +253,7 @@ class MSHR(id: Int) extends Component with ThreeStateIncoherence {
 
 class MSHRFile extends Component {
   val io = new Bundle {
-    val req = (new ioDecoupled) { new MSHRReq }
+    val req = (new ioDecoupled) { new MSHRReq }.flip
 
     val mem_resp_val = Bool(INPUT)
     val mem_resp_tag = Bits(MEM_TAG_BITS, INPUT)
@@ -262,9 +262,9 @@ class MSHRFile extends Component {
 
     val fence_rdy = Bool(OUTPUT)
 
-    val mem_req  = (new ioDecoupled) { new TransactionInit }.flip()
-    val meta_req = (new ioDecoupled) { new MetaArrayArrayReq() }.flip()
-    val data_req   = (new ioDecoupled) { new DataReq() }.flip()
+    val mem_req  = (new ioDecoupled) { new TransactionInit }
+    val meta_req = (new ioDecoupled) { new MetaArrayArrayReq() }
+    val data_req   = (new ioDecoupled) { new DataReq() }
 
     val cpu_resp_val = Bool(OUTPUT)
     val cpu_resp_tag = Bits(DCACHE_TAG_BITS, OUTPUT)
@@ -349,12 +349,12 @@ class MSHRFile extends Component {
 
 class WritebackUnit extends Component {
   val io = new Bundle {
-    val req    = (new ioDecoupled) { new WritebackReq() }
-    val data_req  = (new ioDecoupled) { new DataArrayArrayReq() }.flip()
+    val req    = (new ioDecoupled) { new WritebackReq() }.flip
+    val data_req  = (new ioDecoupled) { new DataArrayArrayReq() }
     val data_resp = Bits(MEM_DATA_BITS, INPUT)
-    val refill_req = (new ioDecoupled) { new TransactionInit }
-    val mem_req   = (new ioDecoupled) { new TransactionInit }.flip
-    val mem_req_data = (new ioDecoupled) { new TransactionInitData }.flip
+    val refill_req = (new ioDecoupled) { new TransactionInit }.flip
+    val mem_req   = (new ioDecoupled) { new TransactionInit }
+    val mem_req_data = (new ioDecoupled) { new TransactionInitData }
   }
 
   val valid = Reg(resetVal = Bool(false))
@@ -391,11 +391,11 @@ class WritebackUnit extends Component {
 
 class FlushUnit(lines: Int) extends Component with ThreeStateIncoherence{
   val io = new Bundle {
-    val req  = (new ioDecoupled) { Bits(width = DCACHE_TAG_BITS) }
-    val resp = (new ioDecoupled) { Bits(width = DCACHE_TAG_BITS) }.flip()
-    val meta_req   = (new ioDecoupled) { new MetaArrayArrayReq() }.flip()
+    val req  = (new ioDecoupled) { Bits(width = DCACHE_TAG_BITS) }.flip
+    val resp = (new ioDecoupled) { Bits(width = DCACHE_TAG_BITS) }
+    val meta_req   = (new ioDecoupled) { new MetaArrayArrayReq() }
     val meta_resp  = (new MetaData).asInput()
-    val wb_req = (new ioDecoupled) { new WritebackReq() }.flip()
+    val wb_req = (new ioDecoupled) { new WritebackReq() }
   }
   
   val s_reset :: s_ready :: s_meta_read :: s_meta_wait :: s_meta_write :: s_done :: Nil = Enum(6) { UFix() }
@@ -444,9 +444,9 @@ class FlushUnit(lines: Int) extends Component with ThreeStateIncoherence{
 
 class MetaDataArray(lines: Int) extends Component {
   val io = new Bundle {
-    val req  = (new ioDecoupled) { new MetaArrayReq() }
+    val req  = (new ioDecoupled) { new MetaArrayReq() }.flip
     val resp = (new MetaData).asOutput()
-    val state_req = (new ioDecoupled) { new MetaArrayReq() }
+    val state_req = (new ioDecoupled) { new MetaArrayReq() }.flip
   }
 
   val permissions_array = Mem(lines){ Bits(width = 2) }
@@ -470,9 +470,9 @@ class MetaDataArray(lines: Int) extends Component {
 
 class MetaDataArrayArray(lines: Int) extends Component {
   val io = new Bundle {
-    val req  = (new ioDecoupled) { new MetaArrayArrayReq() }
+    val req  = (new ioDecoupled) { new MetaArrayArrayReq() }.flip
     val resp = Vec(NWAYS){ (new MetaData).asOutput }
-    val state_req = (new ioDecoupled) { new MetaArrayArrayReq() }
+    val state_req = (new ioDecoupled) { new MetaArrayArrayReq() }.flip
     val way_en = Bits(width = NWAYS, dir = OUTPUT)
   }
 
@@ -501,7 +501,7 @@ class MetaDataArrayArray(lines: Int) extends Component {
 
 class DataArray(lines: Int) extends Component {
   val io = new Bundle {
-    val req  = (new ioDecoupled) { new DataArrayReq() }
+    val req  = (new ioDecoupled) { new DataArrayReq() }.flip
     val resp = Bits(width = MEM_DATA_BITS, dir = OUTPUT)
   }
 
@@ -518,7 +518,7 @@ class DataArray(lines: Int) extends Component {
 
 class DataArrayArray(lines: Int) extends Component {
   val io = new Bundle {
-    val req  = (new ioDecoupled) { new DataArrayArrayReq() }
+    val req  = (new ioDecoupled) { new DataArrayArrayReq() }.flip
     val resp = Vec(NWAYS){ Bits(width = MEM_DATA_BITS, dir = OUTPUT) }
     val way_en = Bits(width = NWAYS, dir = OUTPUT)
   }
diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala
index 30b37603..524e26bb 100644
--- a/rocket/src/main/scala/ptw.scala
+++ b/rocket/src/main/scala/ptw.scala
@@ -7,7 +7,7 @@ import scala.math._;
 
 class ioDmemArbiter(n: Int) extends Bundle
 {
-  val dmem = new ioDmem().flip()
+  val dmem = new ioDmem().flip
   val requestor = Vec(n) { new ioDmem() }
 }
 
@@ -70,9 +70,9 @@ class rocketDmemArbiter(n: Int) extends Component
 
 class ioPTW extends Bundle
 {
-  val itlb = new ioTLB_PTW().flip();
-  val dtlb = new ioTLB_PTW().flip();
-  val dmem = new ioDmem().flip()
+  val itlb = new ioTLB_PTW().flip
+  val dtlb = new ioTLB_PTW().flip
+  val dmem = new ioDmem().flip
   val ptbr = UFix(PADDR_BITS, INPUT);
 }
 
diff --git a/rocket/src/main/scala/queues.scala b/rocket/src/main/scala/queues.scala
index 803b86ef..46f1ddec 100644
--- a/rocket/src/main/scala/queues.scala
+++ b/rocket/src/main/scala/queues.scala
@@ -6,8 +6,8 @@ import Node._;
 class ioQueue[T <: Data](flushable: Boolean)(data: => T) extends Bundle
 {
   val flush = if (flushable) Bool(INPUT) else null
-  val enq   = new ioDecoupled()(data)
-  val deq   = new ioDecoupled()(data).flip
+  val enq   = new ioDecoupled()(data).flip
+  val deq   = new ioDecoupled()(data)
 }
 
 class queue[T <: Data](entries: Int, pipe: Boolean = false, flushable: Boolean = false)(data: => T) extends Component
@@ -66,8 +66,8 @@ object Queue
 class pipereg[T <: Data]()(data: => T) extends Component
 {
   val io = new Bundle {
-    val enq = new ioValid()(data)
-    val deq = new ioValid()(data).flip
+    val enq = new ioPipe()(data)
+    val deq = new ioPipe()(data).flip
   }
 
   //val bits = Reg() { io.enq.bits.clone }
@@ -81,7 +81,7 @@ class pipereg[T <: Data]()(data: => T) extends Component
 
 object Pipe
 {
-  def apply[T <: Data](enq: ioValid[T], latency: Int = 1): ioValid[T] = {
+  def apply[T <: Data](enq: ioPipe[T], latency: Int = 1): ioPipe[T] = {
     val q = (new pipereg) { enq.bits.clone }
     q.io.enq <> enq
     q.io.deq
diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala
index bbb53e83..4b59d022 100644
--- a/rocket/src/main/scala/util.scala
+++ b/rocket/src/main/scala/util.scala
@@ -168,20 +168,20 @@ class Mux1H [T <: Data](n: Int)(gen: => T) extends Component
 
 class ioDecoupled[+T <: Data]()(data: => T) extends Bundle
 {
-  val valid = Bool(INPUT)
-  val ready = Bool(OUTPUT)
-  val bits  = data.asInput
+  val ready = Bool(INPUT)
+  val valid = Bool(OUTPUT)
+  val bits  = data.asOutput
 }
 
-class ioValid[T <: Data]()(data: => T) extends Bundle
+class ioPipe[T <: Data]()(data: => T) extends Bundle
 {
   val valid = Bool(INPUT)
   val bits = data.asInput
 }
 
 class ioArbiter[T <: Data](n: Int)(data: => T) extends Bundle {
-  val in  = Vec(n) { (new ioDecoupled()) { data } }
-  val out = (new ioDecoupled()) { data }.flip()
+  val in  = Vec(n) { (new ioDecoupled()) { data } }.flip
+  val out = (new ioDecoupled()) { data }
 }
 
 class Arbiter[T <: Data](n: Int)(data: => T) extends Component {
@@ -205,9 +205,9 @@ class Arbiter[T <: Data](n: Int)(data: => T) extends Component {
 }
 
 class ioLockingArbiter[T <: Data](n: Int)(data: => T) extends Bundle {
-  val in   = Vec(n) { (new ioDecoupled()) { data } }
+  val in   = Vec(n) { (new ioDecoupled()) { data } }.flip
   val lock = Vec(n) { Bool() }.asInput
-  val out  = (new ioDecoupled()) { data }.flip()
+  val out  = (new ioDecoupled()) { data }
 }
 
 class LockingArbiter[T <: Data](n: Int)(data: => T) extends Component {