riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

clean up ioDecoupled/ioPipe interface

Browse Source
This commit is contained in:
Yunsup Lee
2012-03-01 20:48:46 -08:00
parent 6d03d75835
commit 8678b3d70c
13 changed files with 73 additions and 73 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
rocket/src/main/scala/dpath.scala
View File

@ -16,15 +16,15 @@ class ioDpathImem extends Bundle()
class ioDpathAll extends Bundle()
{
val host = new ioHTIF();
val ctrl = new ioCtrlDpath().flip();
val ctrl = new ioCtrlDpath().flip
val debug = new ioDebug();
val dmem = new ioDmem(List("req_idx", "req_tag", "req_data", "resp_val", "resp_miss", "resp_replay", "resp_type", "resp_tag", "resp_data", "resp_data_subword")).flip();
val dmem = new ioDmem(List("req_idx", "req_tag", "req_data", "resp_val", "resp_miss", "resp_replay", "resp_type", "resp_tag", "resp_data", "resp_data_subword")).flip
val dtlb = new ioDTLB_CPU_req_bundle().asOutput()
val imem = new ioDpathImem();
val ptbr_wen = Bool(OUTPUT);
val ptbr = UFix(PADDR_BITS, OUTPUT);
val fpu = new ioDpathFPU();
val vec_ctrl = new ioCtrlDpathVec().flip()
val vec_ctrl = new ioCtrlDpathVec().flip
val vec_iface = new ioDpathVecInterface()
val vec_imul_req = new io_imul_req
val vec_imul_resp = Bits(hwacha.Constants.SZ_XLEN, INPUT)