riscv/rocket-chip
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pulled submodule commits, uncore sbt standardized

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This commit is contained in:
Henry Cook
2013-08-15 17:07:13 -07:00
parent 6b20556661
commit 85e5ce046f
3 changed files with 4 additions and 4 deletions
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2
src/main/scala/RocketChip.scala
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@@ -255,7 +255,7 @@ class Top extends Module {
val io = new VLSITopIO(HTIF_WIDTH)
val resetSigs = Vec.fill(uc.nTiles){Bool()}
val tileList = (0 until uc.nTiles).map(r => Module(new Tile(_reset = resetSigs(r))(rc)))
val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
val uncore = Module(new Uncore(HTIF_WIDTH, tileList))
var error_mode = Bool(false)

2
src/main/scala/fpga.scala
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@@ -99,7 +99,7 @@ class FPGATop extends Module {
val io = new FPGATopIO(htif_width)
val resetSigs = Vec.fill(uc.nTiles){Bool()}
val tileList = (0 until uc.nTiles).map(r => Module(new Tile(_reset = resetSigs(r))(rc)))
val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
val uncore = Module(new FPGAUncore(htif_width, tileList))
io.debug.error_mode := Bool(false)