From 85e5ce046f848025cf2f20b18b042b46b56fd0af Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@eecs.berkeley.edu>
Date: Thu, 15 Aug 2013 17:07:13 -0700
Subject: [PATCH] pulled submodule commits, uncore sbt standardized

---
 emulator/Makefile               | 4 ++--
 src/main/scala/RocketChip.scala | 2 +-
 src/main/scala/fpga.scala       | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/emulator/Makefile b/emulator/Makefile
index a1fdb639..cbcd5ff8 100644
--- a/emulator/Makefile
+++ b/emulator/Makefile
@@ -18,10 +18,10 @@ DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL))
 CHISEL_ARGS := $(MODEL) --noIoDebug --backend c --targetDir $(base_dir)/emulator/generated-src
 CHISEL_ARGS_DEBUG := $(CHISEL_ARGS)-debug --debug --vcd --ioDebug
 
-generated-src/$(MODEL).cpp: $(base_dir)/riscv-rocket/src/*.scala $(base_dir)/riscv-hwacha/src/*.scala $(base_dir)/chisel/src/main/scala/* $(base_dir)/uncore/src/*.scala $(base_dir)/src/*.scala
+generated-src/$(MODEL).cpp: $(base_dir)/riscv-rocket/src/*.scala $(base_dir)/riscv-hwacha/src/*.scala $(base_dir)/chisel/src/main/scala/* $(base_dir)/uncore/src/main/scala/*.scala $(base_dir)/src/*.scala
 	cd $(base_dir)/sbt && $(SBT) "project referencechip" "elaborate $(CHISEL_ARGS)"
 
-generated-src-debug/$(MODEL).cpp: $(base_dir)/riscv-rocket/src/*.scala $(base_dir)/riscv-hwacha/src/*.scala $(base_dir)/chisel/src/main/scala/* $(base_dir)/uncore/src/*.scala $(base_dir)/src/*.scala
+generated-src-debug/$(MODEL).cpp: $(base_dir)/riscv-rocket/src/*.scala $(base_dir)/riscv-hwacha/src/*.scala $(base_dir)/chisel/src/main/scala/* $(base_dir)/uncore/src/main/*.scala $(base_dir)/src/*.scala
 	cd $(base_dir)/sbt && $(SBT) "project referencechip" "elaborate $(CHISEL_ARGS_DEBUG)"
 
 $(MODEL).o: %.o: generated-src/%.cpp
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 5c13e6a4..81054ea6 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -255,7 +255,7 @@ class Top extends Module {
   val io = new VLSITopIO(HTIF_WIDTH)
 
   val resetSigs = Vec.fill(uc.nTiles){Bool()}
-  val tileList = (0 until uc.nTiles).map(r => Module(new Tile(_reset = resetSigs(r))(rc)))
+  val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
   val uncore = Module(new Uncore(HTIF_WIDTH, tileList))
 
   var error_mode = Bool(false)
diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala
index 7844da14..d991cc8f 100644
--- a/src/main/scala/fpga.scala
+++ b/src/main/scala/fpga.scala
@@ -99,7 +99,7 @@ class FPGATop extends Module {
   val io = new FPGATopIO(htif_width)
 
   val resetSigs = Vec.fill(uc.nTiles){Bool()}
-  val tileList = (0 until uc.nTiles).map(r => Module(new Tile(_reset = resetSigs(r))(rc)))
+  val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
   val uncore = Module(new FPGAUncore(htif_width, tileList))
 
   io.debug.error_mode := Bool(false)