rocket: give itim and dtim a compatible field for drivers to match

src/main/scala/rocket/ICache.scala

@@ -40,7 +40,7 @@ class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parame
   val masterNode = TLClientNode(TLClientParameters(name = s"Core ${hartid} ICache"))
 
   val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes
-  val device = new SimpleDevice("itim", Nil)
+  val device = new SimpleDevice("itim", Seq("sifive,itim0"))
   val slaveNode = icacheParams.itimAddr.map { itimAddr =>
     val wordBytes = icacheParams.fetchBytes
     TLManagerNode(Seq(TLManagerPortParameters(

src/main/scala/rocket/ScratchpadSlavePort.scala

@@ -15,7 +15,7 @@ import util._
 
 class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends LazyModule
     with HasCoreParameters {
-  val device = new SimpleDevice("dtim", Nil)
+  val device = new SimpleDevice("dtim", Seq("sifive,dtim0"))
   val node = TLManagerNode(Seq(TLManagerPortParameters(
     Seq(TLManagerParameters(
       address            = List(address),