From 852f03282f01670fe31154c9f168193c7fe1f764 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 28 Jun 2017 12:00:44 -0700 Subject: [PATCH] rocket: give itim and dtim a compatible field for drivers to match --- src/main/scala/rocket/ICache.scala | 2 +- src/main/scala/rocket/ScratchpadSlavePort.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index cd4bed4d..2a7828cb 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -40,7 +40,7 @@ class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parame val masterNode = TLClientNode(TLClientParameters(name = s"Core ${hartid} ICache")) val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes - val device = new SimpleDevice("itim", Nil) + val device = new SimpleDevice("itim", Seq("sifive,itim0")) val slaveNode = icacheParams.itimAddr.map { itimAddr => val wordBytes = icacheParams.fetchBytes TLManagerNode(Seq(TLManagerPortParameters( diff --git a/src/main/scala/rocket/ScratchpadSlavePort.scala b/src/main/scala/rocket/ScratchpadSlavePort.scala index f2681fb2..545b0d0b 100644 --- a/src/main/scala/rocket/ScratchpadSlavePort.scala +++ b/src/main/scala/rocket/ScratchpadSlavePort.scala @@ -15,7 +15,7 @@ import util._ class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends LazyModule with HasCoreParameters { - val device = new SimpleDevice("dtim", Nil) + val device = new SimpleDevice("dtim", Seq("sifive,dtim0")) val node = TLManagerNode(Seq(TLManagerPortParameters( Seq(TLManagerParameters( address = List(address),