riscv/rocket-chip
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rocket: give itim and dtim a compatible field for drivers to match

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This commit is contained in:
Wesley W. Terpstra 2017-06-28 12:00:44 -07:00
parent 6c2b770605
commit 852f03282f
2 changed files with 2 additions and 2 deletions
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2
src/main/scala/rocket/ICache.scala
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@ -40,7 +40,7 @@ class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parame
val masterNode = TLClientNode(TLClientParameters(name = s"Core ${hartid} ICache")) val masterNode = TLClientNode(TLClientParameters(name = s"Core ${hartid} ICache"))
val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes
val device = new SimpleDevice("itim", Nil) val device = new SimpleDevice("itim", Seq("sifive,itim0"))
val slaveNode = icacheParams.itimAddr.map { itimAddr => val slaveNode = icacheParams.itimAddr.map { itimAddr =>
val wordBytes = icacheParams.fetchBytes val wordBytes = icacheParams.fetchBytes
TLManagerNode(Seq(TLManagerPortParameters( TLManagerNode(Seq(TLManagerPortParameters(

2
src/main/scala/rocket/ScratchpadSlavePort.scala
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@ -15,7 +15,7 @@ import util._
class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends LazyModule class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends LazyModule
with HasCoreParameters { with HasCoreParameters {
val device = new SimpleDevice("dtim", Nil) val device = new SimpleDevice("dtim", Seq("sifive,dtim0"))
val node = TLManagerNode(Seq(TLManagerPortParameters( val node = TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters( Seq(TLManagerParameters(
address = List(address), address = List(address),