riscv/rocket-chip
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remove implicit modulo addressing in FPU (#44)

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Colin Schmidt 2016-06-09 11:33:33 -07:00 committed by Andrew Waterman
parent e3c17b5f74
commit 8516e38eb2
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/fpu.scala
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@ -561,7 +561,7 @@ class FPU(implicit p: Parameters) extends CoreModule()(p) {
} }
val waddr = Mux(divSqrt_wen, divSqrt_waddr, winfo(0)(4,0).toUInt) val waddr = Mux(divSqrt_wen, divSqrt_waddr, winfo(0)(4,0).toUInt)
val wsrc = (winfo(0) >> 6) val wsrc = (winfo(0) >> 6)(log2Up(pipes.size) - 1,0)
val wcp = winfo(0)(6+log2Up(pipes.size)) val wcp = winfo(0)(6+log2Up(pipes.size))
val wdata = Mux(divSqrt_wen, divSqrt_wdata, Vec(pipes.map(_.res.data))(wsrc)) val wdata = Mux(divSqrt_wen, divSqrt_wdata, Vec(pipes.map(_.res.data))(wsrc))
val wexc = Vec(pipes.map(_.res.exc))(wsrc) val wexc = Vec(pipes.map(_.res.exc))(wsrc)