From 8516e38eb25b314990c3005f1dd7c2db74b4fdc8 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Thu, 9 Jun 2016 11:33:33 -0700 Subject: [PATCH] remove implicit modulo addressing in FPU (#44) --- rocket/src/main/scala/fpu.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala index b7c72945..107f93bd 100644 --- a/rocket/src/main/scala/fpu.scala +++ b/rocket/src/main/scala/fpu.scala @@ -561,7 +561,7 @@ class FPU(implicit p: Parameters) extends CoreModule()(p) { } val waddr = Mux(divSqrt_wen, divSqrt_waddr, winfo(0)(4,0).toUInt) - val wsrc = (winfo(0) >> 6) + val wsrc = (winfo(0) >> 6)(log2Up(pipes.size) - 1,0) val wcp = winfo(0)(6+log2Up(pipes.size)) val wdata = Mux(divSqrt_wen, divSqrt_wdata, Vec(pipes.map(_.res.data))(wsrc)) val wexc = Vec(pipes.map(_.res.exc))(wsrc)