riscv/rocket-chip
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coreplex => subsystem

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This commit is contained in:
Henry Cook
2018-01-12 12:29:27 -08:00
parent 32c5c3c04d
commit 8462ea3d5b
45 changed files with 114 additions and 114 deletions
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src/main/scala/tile/Interrupts.scala
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@ -18,7 +18,7 @@ class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) {
val lip = Vec(coreParams.nLocalInterrupts, Bool())
}
// Use diplomatic interrupts to external interrupts from the coreplex into the tile
// Use diplomatic interrupts to external interrupts from the subsystem into the tile
trait HasExternalInterrupts { this: BaseTile =>
val intInwardNode = intXbar.intnode
@ -50,7 +50,7 @@ trait HasExternalInterrupts { this: BaseTile =>
// TODO: the order of the following two functions must match, and
// also match the order which things are connected to the
// per-tile crossbar in coreplex.HasRocketTiles
// per-tile crossbar in subsystem.HasRocketTiles
// debug, msip, mtip, meip, seip, lip offsets in CSRs
def csrIntMap: List[Int] = {