riscv/rocket-chip
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coreplex => subsystem

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This commit is contained in:
Henry Cook
2018-01-12 12:29:27 -08:00
parent 32c5c3c04d
commit 8462ea3d5b
45 changed files with 114 additions and 114 deletions
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8
src/main/scala/groundtest/Coreplex.scala
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@ -7,7 +7,7 @@ import Chisel._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.coreplex._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.tile._
@ -15,7 +15,7 @@ import scala.math.max
case object TileId extends Field[Int]
class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
class GroundTestSubsystem(implicit p: Parameters) extends BaseSubsystem
with HasMasterAXI4MemPort
with HasPeripheryTestRAMSlave
with HasInterruptBus {
@ -37,10 +37,10 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), true, false, pbus.beatBytes))
pbusRAM.node := pbus.toVariableWidthSlaves
override lazy val module = new GroundTestCoreplexModule(this)
override lazy val module = new GroundTestSubsystemModule(this)
}
class GroundTestCoreplexModule[+L <: GroundTestCoreplex](_outer: L) extends BaseCoreplexModule(_outer)
class GroundTestSubsystemModule[+L <: GroundTestSubsystem](_outer: L) extends BaseSubsystemModule(_outer)
with HasMasterAXI4MemPortModuleImp {
val success = IO(Bool(OUTPUT))