64 lines
2.1 KiB
Scala
64 lines
2.1 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.groundtest
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.tile._
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import scala.math.max
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case object TileId extends Field[Int]
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class GroundTestSubsystem(implicit p: Parameters) extends BaseSubsystem
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with HasMasterAXI4MemPort
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with HasPeripheryTestRAMSlave
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with HasInterruptBus {
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val tileParams = p(GroundTestTilesKey)
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val tiles = tileParams.zipWithIndex.map { case(c, i) => LazyModule(
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c.build(i, p.alterPartial {
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case TileKey => c
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case SharedMemoryTLEdge => sbus.busView
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})
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)}
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tiles.flatMap(_.dcacheOpt).foreach { dc =>
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sbus.fromTile(None) { implicit p => TileMasterPortParams(addBuffers = 1).adapt(this)(dc.node) }
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}
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// No PLIC in ground test; so just sink the interrupts to nowhere
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IntSinkNode(IntSinkPortSimple()) := ibus.toPLIC
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val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), true, false, pbus.beatBytes))
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pbusRAM.node := pbus.toVariableWidthSlaves
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override lazy val module = new GroundTestSubsystemModule(this)
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}
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class GroundTestSubsystemModule[+L <: GroundTestSubsystem](_outer: L) extends BaseSubsystemModule(_outer)
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with HasMasterAXI4MemPortModuleImp {
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val success = IO(Bool(OUTPUT))
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outer.tiles.zipWithIndex.map { case(t, i) => t.module.constants.hartid := UInt(i) }
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val status = DebugCombiner(outer.tiles.map(_.module.status))
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success := status.finished
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}
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/** Adds a SRAM to the system for testing purposes. */
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trait HasPeripheryTestRAMSlave extends HasPeripheryBus {
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val testram = LazyModule(new TLRAM(AddressSet(0x52000000, 0xfff), true, true, pbus.beatBytes))
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testram.node := pbus.toVariableWidthSlaves
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}
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/** Adds a fuzzing master to the system for testing purposes. */
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trait HasPeripheryTestFuzzMaster extends HasPeripheryBus {
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val fuzzer = LazyModule(new TLFuzzer(5000))
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pbus.bufferFromMasters := fuzzer.node
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}
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