riscv/rocket-chip
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Chisel3 compatibility fixes

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This commit is contained in:
Andrew Waterman
2015-09-30 14:36:26 -07:00
parent a7c908cb83
commit 833909a2b5
6 changed files with 16 additions and 16 deletions
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4
rocket/src/main/scala/tlb.scala
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@ -33,7 +33,7 @@ class CAMIO extends TLBBundle {
class RocketCAM extends TLBModule {
val io = new CAMIO
val cam_tags = Mem(Bits(width = camTagBits), entries)
val cam_tags = Mem(entries, Bits(width = camTagBits))
val vb_array = Reg(init=Bits(0, entries))
when (io.write) {
@ -109,7 +109,7 @@ class TLB extends TLBModule {
val r_req = Reg(new TLBReq)
val tag_cam = Module(new RocketCAM)
val tag_ram = Mem(io.ptw.resp.bits.pte.ppn, entries)
val tag_ram = Mem(entries, io.ptw.resp.bits.pte.ppn)
val lookup_tag = Cat(io.req.bits.asid, io.req.bits.vpn).toUInt
tag_cam.io.tag := lookup_tag