From 833909a2b544b4413a6c4bb6121b789cc61ba705 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 30 Sep 2015 14:36:26 -0700 Subject: [PATCH] Chisel3 compatibility fixes --- rocket/src/main/scala/btb.scala | 18 +++++++++--------- rocket/src/main/scala/fpu.scala | 2 +- rocket/src/main/scala/nbdcache.scala | 2 +- rocket/src/main/scala/ptw.scala | 4 ++-- rocket/src/main/scala/rocket.scala | 2 +- rocket/src/main/scala/tlb.scala | 4 ++-- 6 files changed, 16 insertions(+), 16 deletions(-) diff --git a/rocket/src/main/scala/btb.scala b/rocket/src/main/scala/btb.scala index d687c22e..df6c433f 100644 --- a/rocket/src/main/scala/btb.scala +++ b/rocket/src/main/scala/btb.scala @@ -69,7 +69,7 @@ class BHT(nbht: Int) { when (mispredict) { history := Cat(taken, d.history(nbhtbits-1,1)) } } - private val table = Mem(UInt(width = 2), nbht) + private val table = Mem(nbht, UInt(width = 2)) val history = Reg(UInt(width = nbhtbits)) } @@ -134,18 +134,18 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete } val idxValid = Reg(init=UInt(0, entries)) - val idxs = Mem(UInt(width=matchBits), entries) - val idxPages = Mem(UInt(width=log2Up(nPages)), entries) - val tgts = Mem(UInt(width=matchBits), entries) - val tgtPages = Mem(UInt(width=log2Up(nPages)), entries) - val pages = Mem(UInt(width=vaddrBits-matchBits), nPages) + val idxs = Mem(entries, UInt(width=matchBits)) + val idxPages = Mem(entries, UInt(width=log2Up(nPages))) + val tgts = Mem(entries, UInt(width=matchBits)) + val tgtPages = Mem(entries, UInt(width=log2Up(nPages))) + val pages = Mem(nPages, UInt(width=vaddrBits-matchBits)) val pageValid = Reg(init=UInt(0, nPages)) val idxPagesOH = idxPages.map(UIntToOH(_)(nPages-1,0)) val tgtPagesOH = tgtPages.map(UIntToOH(_)(nPages-1,0)) - val useRAS = Reg(Vec(Bool(), entries)) - val isJump = Reg(Vec(Bool(), entries)) - val brIdx = Mem(UInt(width=log2Up(params(FetchWidth))), entries) + val useRAS = Reg(Vec(entries, Bool())) + val isJump = Reg(Vec(entries, Bool())) + val brIdx = Mem(entries, UInt(width=log2Up(params(FetchWidth)))) private def page(addr: UInt) = addr >> matchBits private def pageMatch(addr: UInt) = { diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala index 10d657a2..daecb199 100644 --- a/rocket/src/main/scala/fpu.scala +++ b/rocket/src/main/scala/fpu.scala @@ -382,7 +382,7 @@ class FPU extends CoreModule val load_wb_data_recoded = Mux(load_wb_single, Cat(SInt(-1, 32), rec_s), rec_d) // regfile - val regfile = Mem(Bits(width = 65), 32) + val regfile = Mem(32, Bits(width = 65)) when (load_wb) { regfile(load_wb_tag) := load_wb_data_recoded if (EnableCommitLog) { diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index d1560cde..bfbcdb11 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -387,7 +387,7 @@ class MSHRFile extends L1HellaCacheModule { val sdq_alloc_id = PriorityEncoder(~sdq_val(sdqDepth-1,0)) val sdq_rdy = !sdq_val.andR val sdq_enq = io.req.valid && io.req.ready && cacheable && isWrite(io.req.bits.cmd) - val sdq = Mem(io.req.bits.data, sdqDepth) + val sdq = Mem(sdqDepth, io.req.bits.data) when (sdq_enq) { sdq(sdq_alloc_id) := io.req.bits.data } val idxMatch = Wire(Vec(Bool(), nMSHRs)) diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala index 1a49cee0..084eee2f 100644 --- a/rocket/src/main/scala/ptw.scala +++ b/rocket/src/main/scala/ptw.scala @@ -87,8 +87,8 @@ class PTW(n: Int) extends CoreModule val plru = new PseudoLRU(size) val valid = Reg(Vec(Bool(), size)) val validBits = valid.toBits - val tags = Mem(UInt(width = paddrBits), size) - val data = Mem(UInt(width = ppnBits), size) + val tags = Mem(size, UInt(width = paddrBits)) + val data = Mem(size, UInt(width = ppnBits)) val hits = Vec(tags.map(_ === pte_addr)).toBits & validBits val hit = hits.orR diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala index ccc3950e..30e33d0e 100644 --- a/rocket/src/main/scala/rocket.scala +++ b/rocket/src/main/scala/rocket.scala @@ -571,7 +571,7 @@ class Rocket extends CoreModule } class RegFile { - private val rf = Mem(UInt(width = 64), 31) + private val rf = Mem(31, UInt(width = 64)) private val reads = collection.mutable.ArrayBuffer[(UInt,UInt)]() private var canRead = true def read(addr: UInt) = { diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala index ce02f8ee..330c5989 100644 --- a/rocket/src/main/scala/tlb.scala +++ b/rocket/src/main/scala/tlb.scala @@ -33,7 +33,7 @@ class CAMIO extends TLBBundle { class RocketCAM extends TLBModule { val io = new CAMIO - val cam_tags = Mem(Bits(width = camTagBits), entries) + val cam_tags = Mem(entries, Bits(width = camTagBits)) val vb_array = Reg(init=Bits(0, entries)) when (io.write) { @@ -109,7 +109,7 @@ class TLB extends TLBModule { val r_req = Reg(new TLBReq) val tag_cam = Module(new RocketCAM) - val tag_ram = Mem(io.ptw.resp.bits.pte.ppn, entries) + val tag_ram = Mem(entries, io.ptw.resp.bits.pte.ppn) val lookup_tag = Cat(io.req.bits.asid, io.req.bits.vpn).toUInt tag_cam.io.tag := lookup_tag