riscv/rocket-chip
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Chisel3 compatibility fixes

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This commit is contained in:
Andrew Waterman
2015-09-30 14:36:26 -07:00
parent a7c908cb83
commit 833909a2b5
6 changed files with 16 additions and 16 deletions
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rocket/src/main/scala/rocket.scala
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@ -571,7 +571,7 @@ class Rocket extends CoreModule
}
class RegFile {
private val rf = Mem(UInt(width = 64), 31)
private val rf = Mem(31, UInt(width = 64))
private val reads = collection.mutable.ArrayBuffer[(UInt,UInt)]()
private var canRead = true
def read(addr: UInt) = {