riscv/rocket-chip
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Chisel3 compatibility fixes

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This commit is contained in:
Andrew Waterman
2015-09-30 14:36:26 -07:00
parent a7c908cb83
commit 833909a2b5
6 changed files with 16 additions and 16 deletions
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4
rocket/src/main/scala/ptw.scala
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@ -87,8 +87,8 @@ class PTW(n: Int) extends CoreModule
val plru = new PseudoLRU(size)
val valid = Reg(Vec(Bool(), size))
val validBits = valid.toBits
val tags = Mem(UInt(width = paddrBits), size)
val data = Mem(UInt(width = ppnBits), size)
val tags = Mem(size, UInt(width = paddrBits))
val data = Mem(size, UInt(width = ppnBits))
val hits = Vec(tags.map(_ === pte_addr)).toBits & validBits
val hit = hits.orR