riscv/rocket-chip
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Chisel3 compatibility fixes

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This commit is contained in:
Andrew Waterman
2015-09-30 14:36:26 -07:00
parent a7c908cb83
commit 833909a2b5
6 changed files with 16 additions and 16 deletions
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2
rocket/src/main/scala/nbdcache.scala
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@ -387,7 +387,7 @@ class MSHRFile extends L1HellaCacheModule {
val sdq_alloc_id = PriorityEncoder(~sdq_val(sdqDepth-1,0))
val sdq_rdy = !sdq_val.andR
val sdq_enq = io.req.valid && io.req.ready && cacheable && isWrite(io.req.bits.cmd)
val sdq = Mem(io.req.bits.data, sdqDepth)
val sdq = Mem(sdqDepth, io.req.bits.data)
when (sdq_enq) { sdq(sdq_alloc_id) := io.req.bits.data }
val idxMatch = Wire(Vec(Bool(), nMSHRs))