riscv/rocket-chip
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Chisel3 compatibility fixes

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This commit is contained in:
Andrew Waterman
2015-09-30 14:36:26 -07:00
parent a7c908cb83
commit 833909a2b5
6 changed files with 16 additions and 16 deletions
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2
rocket/src/main/scala/fpu.scala
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@ -382,7 +382,7 @@ class FPU extends CoreModule
val load_wb_data_recoded = Mux(load_wb_single, Cat(SInt(-1, 32), rec_s), rec_d)
// regfile
val regfile = Mem(Bits(width = 65), 32)
val regfile = Mem(32, Bits(width = 65))
when (load_wb) {
regfile(load_wb_tag) := load_wb_data_recoded
if (EnableCommitLog) {