riscv/rocket-chip
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coreplex: unconditionally insert a Splitter between tiles and l1tol2

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This commit is contained in:
Wesley W. Terpstra
2017-05-19 17:55:57 -07:00
parent d002cec6ac
commit 81d372137a
3 changed files with 10 additions and 7 deletions
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4
src/main/scala/groundtest/Coreplex.scala
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@ -24,7 +24,7 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex {
case TileId => i
case CacheBlockOffsetBits => log2Up(site(CacheBlockBytes))
case AmoAluOperandBits => site(XLen)
case SharedMemoryTLEdge => l1tol2.node.edgesIn(0)
case SharedMemoryTLEdge => tile_splitter.node.edgesIn(0)
case TLId => "L1toL2"
case TLKey("L1toL2") =>
TileLinkParameters(
@ -41,7 +41,7 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex {
}
val fixer = LazyModule(new TLFIFOFixer)
l1tol2.node :=* fixer.node
tile_splitter.node :=* fixer.node
tiles.foreach { fixer.node :=* _.masterNode }
val cbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, cbus_beatBytes))