60 lines
2.1 KiB
Scala
60 lines
2.1 KiB
Scala
// See LICENSE.SiFive for license details.
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package groundtest
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import Chisel._
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import config._
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import diplomacy._
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import coreplex._
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import rocket._
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import tile._
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import uncore.agents._
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import uncore.coherence._
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import uncore.devices._
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import uncore.tilelink._
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import uncore.tilelink2._
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import uncore.util._
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import scala.math.max
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case object TileId extends Field[Int]
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class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex {
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val tiles = List.tabulate(p(NTiles)) { i =>
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LazyModule(new GroundTestTile()(p.alter { (site, here, up) => {
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case TileId => i
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case CacheBlockOffsetBits => log2Up(site(CacheBlockBytes))
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case AmoAluOperandBits => site(XLen)
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case SharedMemoryTLEdge => tile_splitter.node.edgesIn(0)
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case TLId => "L1toL2"
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case TLKey("L1toL2") =>
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TileLinkParameters(
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coherencePolicy = new MESICoherence(new NullRepresentation(site(NTiles))),
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nManagers = site(BankedL2Config).nBanks + 1,
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nCachingClients = 1,
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nCachelessClients = 1,
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maxClientXacts = site(GroundTestKey).map(_.maxXacts).reduce(max(_, _)),
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maxClientsPerPort = site(GroundTestKey).map(_.uncached).sum,
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maxManagerXacts = 8,
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dataBeats = (8 * site(CacheBlockBytes)) / site(XLen),
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dataBits = site(CacheBlockBytes)*8)
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}}))
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}
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val fixer = LazyModule(new TLFIFOFixer)
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tile_splitter.node :=* fixer.node
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tiles.foreach { fixer.node :=* _.masterNode }
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val cbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, cbus_beatBytes))
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cbusRAM.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
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override lazy val module = new GroundTestCoreplexModule(this, () => new GroundTestCoreplexBundle(this))
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}
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class GroundTestCoreplexBundle[+L <: GroundTestCoreplex](_outer: L) extends BaseCoreplexBundle(_outer) {
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val success = Bool(OUTPUT)
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}
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class GroundTestCoreplexModule[+L <: GroundTestCoreplex, +B <: GroundTestCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io) {
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io.success := outer.tiles.map(_.module.io.success).reduce(_&&_)
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}
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