diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala
index 6f357c0d..7528cead 100644
--- a/rocket/src/main/scala/dpath_util.scala
+++ b/rocket/src/main/scala/dpath_util.scala
@@ -242,6 +242,7 @@ class PCR(implicit conf: RocketConfiguration) extends Module
       reg_status.s64 := true
       reg_status.u64 := true
       reg_status.zero := 0
+      if (!conf.vm) reg_status.vm := false
       if (conf.rocc.isEmpty) reg_status.er := false
       if (!conf.fpu) reg_status.ef := false
     }
diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala
index 022fbf23..7786823b 100644
--- a/rocket/src/main/scala/tile.scala
+++ b/rocket/src/main/scala/tile.scala
@@ -7,6 +7,7 @@ import Util._
 case class RocketConfiguration(tl: TileLinkConfiguration,
                                icache: ICacheConfig, dcache: DCacheConfig,
                                fpu: Boolean, rocc: Option[RocketConfiguration => RoCC] = None,
+                               vm: Boolean = true,
                                fastLoadWord: Boolean = true,
                                fastLoadByte: Boolean = false,
                                fastMulDiv: Boolean = true)