riscv/rocket-chip
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clean up incoherent and probe flags

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This commit is contained in:
Henry Cook
2015-03-12 16:22:14 -07:00
parent dcc84c4dd3
commit 8181262419
3 changed files with 32 additions and 29 deletions
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uncore/src/main/scala/uncore.scala
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@ -73,7 +73,7 @@ trait HasCoherenceAgentWiringHelpers {
trait HasInnerTLIO extends CoherenceAgentBundle {
val inner = Bundle(new TileLinkIO)(innerTLParams).flip
val incoherent = Vec.fill(nClients){Bool()}.asInput
val incoherent = Vec.fill(nCoherentClients){Bool()}.asInput
def iacq(dummy: Int = 0) = inner.acquire.bits.payload
def iprb(dummy: Int = 0) = inner.probe.bits.payload
def irel(dummy: Int = 0) = inner.release.bits.payload