riscv/rocket-chip
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Work around Chisel2 bug

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This code is correct, but Chisel2 erroneously flags it as a Chisel3
compatibility error because it looks like Vec(Reg) when factor=1.
This commit is contained in:
Andrew Waterman 2016-05-26 12:37:31 -07:00
parent 22568de5f3
commit 8139f71dfb
1 changed files with 3 additions and 10 deletions
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13
uncore/src/main/scala/converters.scala
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@ -878,9 +878,6 @@ class TileLinkIOWidener(innerTLId: String, outerTLId: String)
val gnt_client_id = Reg(UInt(width = outerClientIdBits)) val gnt_client_id = Reg(UInt(width = outerClientIdBits))
val gnt_manager_id = Reg(UInt(width = outerManagerIdBits)) val gnt_manager_id = Reg(UInt(width = outerManagerIdBits))
val gnt_data = Reg(UInt(width = outerDataBits)) val gnt_data = Reg(UInt(width = outerDataBits))
val gnt_data_vec = Vec.tabulate(factor) { i =>
gnt_data(innerDataBits * (i + 1) - 1, innerDataBits * i)
}
when (io.out.grant.fire() && stretch) { when (io.out.grant.fire() && stretch) {
gnt_data := ognt.data gnt_data := ognt.data
@ -892,12 +889,8 @@ class TileLinkIOWidener(innerTLId: String, outerTLId: String)
when (send_done) { returning_data := Bool(false) } when (send_done) { returning_data := Bool(false) }
def select_data(data: UInt, sel: UInt): UInt = { def select_data(data: UInt, sel: UInt): UInt =
val data_vec = Vec.tabulate(factor) { i => data >> (sel << log2Up(innerDataBits))
data(innerDataBits * (i + 1) - 1, innerDataBits * i)
}
data_vec(sel)
}
val gnt_switch = smallget_switch(ognt.client_xact_id) val gnt_switch = smallget_switch(ognt.client_xact_id)
@ -907,7 +900,7 @@ class TileLinkIOWidener(innerTLId: String, outerTLId: String)
client_xact_id = gnt_client_id, client_xact_id = gnt_client_id,
manager_xact_id = gnt_manager_id, manager_xact_id = gnt_manager_id,
addr_beat = Cat(gnt_beat, send_idx), addr_beat = Cat(gnt_beat, send_idx),
data = gnt_data_vec(send_idx)) data = select_data(gnt_data, send_idx))
val get_grant = Grant( val get_grant = Grant(
is_builtin_type = Bool(true), is_builtin_type = Bool(true),