riscv/rocket-chip
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rocket: include hartid in cache master names

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This commit is contained in:
Wesley W. Terpstra
2017-06-02 15:29:30 -07:00
parent d25ad10592
commit 80c63c0da6
4 changed files with 12 additions and 11 deletions
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src/main/scala/rocket/DCache.scala
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@ -39,7 +39,7 @@ class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
}
}
class DCache(val scratch: () => Option[AddressSet] = () => None)(implicit p: Parameters) extends HellaCache()(p) {
class DCache(hartid: Int, val scratch: () => Option[AddressSet] = () => None)(implicit p: Parameters) extends HellaCache(hartid)(p) {
override lazy val module = new DCacheModule(this)
}